CCS/TMS320C6670: how to do two X2 SRIO ?

Tool/software: Code Composer Studio

Hi , I have a custom board using 6670.6670 connect to two FPGA ,6670 SRIO lane 0 and lane1 connect to FPGA1,lane 2 and lane 3 connect to FPGA 2.

SRIO ref_clk is 250MHz,serial rate is 3.125Gbps. I wang to set two X2 mode. I use  SRIO_LoopbackDioIsrexampleproject demo.

        // Set MPY to 6.25x
        CSL_BootCfgSetSRIOSERDESConfigPLL (0x233);

        //3.125G
        /* Configure the SRIO SERDES Receive Configuration. */
        CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x00440495);
        CSL_BootCfgSetSRIOSERDESRxConfig (1, 0x00440495);
        CSL_BootCfgSetSRIOSERDESRxConfig (2, 0x00440495);
        CSL_BootCfgSetSRIOSERDESRxConfig (3, 0x00440495);

        /* Configure the SRIO SERDES Transmit Configuration. */
        CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00180795);
        CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x00080795);
        CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x00180795);
        CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x00080795);

        /* Configure the path mode for the ports. */
        for(i = 0; i < 4; i++)
            CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 3);

This will result  DSP can transmit SWRITE packet to FPGA1,but cannot receive SWRITE packet from FPGA1.

However,DSP can receive SWRITE packet from FPGA2.

I dont know how to cimplement two X2 mode , please help me.

Regards,

Tian