AM5728: PLL_CONFIGURATION2 register settings

shigehiro tsuda

Part Number: AM5728

Hi,

Does the bit field of the following registers need to be set?

Table 11-45. PLL_CONFIGURATION 2
DPLL_VIDEO1 _MAIN _ L 3
RESERVED bit 1-3

It seems that the linux code changes depending on the frequency.
linux\drivers\gpu\drm\omapdrm\dss\pll.c

int dss_pll_write_config_type_b(struct dss_pll *pll,
const struct dss_pll_clock_info *cinfo)
{

...

/* PLL_SELFREQDCO */
if (cinfo->clkdco > hw->clkdco_low)
l = FLD_MOD(l, 0x4, 3, 1);
else
l = FLD_MOD(l, 0x2, 3, 1);
writel_relaxed(l, base + PLL_CONFIGURATION2);

.....

}

Best Regards,
Shigehiro Tsuda

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

Hi,

Please read section 11.1.3.3 in the AM572x TRM Rev. I.

0 shigehiro tsuda over 7 years ago in reply to Biser Gatchev-XID

Mastermind 9490 points

Hi Biser,

Thank you for quick reply.

I confirmed the section 11.1.3.3 in the AM572x TRM Rev. I.
However, other than that section, it does not explain the setting of the reserve bit [1..3] of the PLL_CONFIGURATION2 register in AM572x TRM.

When I dumped this register during LCD display on linux, it seemed to be set to bit 3.
Dump result:
address 0x58004310 read value 0x00616008

Sorry, I reviewed the code of linux kernel.
The video dpll was executing dss_pll_write_config_type_a ().
It seems to be the following select.

int dss_pll_write_config_type_a(struct dss_pll *pll,
const struct dss_pll_clock_info *cinfo)
{

...

l = readl_relaxed(base + PLL_CONFIGURATION2);
if (hw->has_freqsel) {
u32 f = cinfo->fint < 1000000 ? 0x3 :
cinfo->fint < 1250000 ? 0x4 :
cinfo->fint < 1500000 ? 0x5 :
cinfo->fint < 1750000 ? 0x6 :
0x7;

l = FLD_MOD(l, f, 4, 1); /* PLL_FREQSEL */
} else if (hw->has_selfreqdco) {
u32 f = cinfo->clkdco < hw->clkdco_low ? 0x2 : 0x4;

l = FLD_MOD(l, f, 3, 1); /* PLL_SELFREQDCO */
}

..
}

Best Regards,
Shigehiro Tsuda

0 Biser Gatchev-XID over 7 years ago in reply to shigehiro tsuda

TI__Guru**** 393215 points

Bits [3:1] of PLL_CONFIGURATION2 are marked as reserved and read-only in the TRM. They should not be modified by user code.

0 Biser Gatchev-XID over 7 years ago in reply to Biser Gatchev-XID

TI__Guru**** 393215 points

I have also asked the factory team to comment on this. They will respond here.

0 shigehiro tsuda over 7 years ago in reply to Biser Gatchev-XID

Mastermind 9490 points

Hi Biser,

Thank you for quick reply.
Is there any update information from your factory team?

Best Regards,
Shigehiro Tsuda

0 Manisha Agrawal over 7 years ago in reply to Biser Gatchev-XID

TI__Mastermind 22946 points

Hi Shigehiro,

Only the bits mentioned in the TRM needs to be set.

The PLL code originates from older devices (OMAP3 times), and has been expanded since. So apparently there are some bits that are now reserved but were needed by those older devices.

Regards,
Manisha

0 shigehiro tsuda over 7 years ago in reply to Manisha Agrawal

Mastermind 9490 points

Hi Manisha,

Thank you for quick reply.

I understood that this bit does not need to be set.
I will reply to our customer.

Thanks for your support.

Best Regards,
Shigehiro Tsuda

0 Pavel Botev over 7 years ago in reply to shigehiro tsuda

TI__Guru**** 170625 points

Shigehiro,

I also think we have a SW bug in the driver. Indeed TRM seems correct, these bits [3:1] should be reserved for AM572x DPLL_VIDEO1/2 PLL_CONFIGURATION2 register, thus not been written by the driver.

linux-kernel/drivers/gpu/drm/omapdrm/dss/dsi.c

static const struct dss_pll_hw dss_omap5_dsi_pll_hw = {
.type = DSS_PLL_TYPE_A,
...

.has_freqsel = false,
- .has_selfreqdco = true,
+ .has_selfreqdco = false,
.has_refsel = true,
};

Regards,
Pavel

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AM5728: PLL_CONFIGURATION2 register settings