• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 461 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM3352: Pixel clock slew rate setting

Gunter Schmer
Genius 14352 points

Part Number: AM3352

Hi,

a customer has EMI issues on AM3352 PCLK (harmonics of the PCLK pixel clock at 25MHz) and is trying to mititgate with series reisistor and setting the slew rate in the register for the PCLK.

We are looking at the register

conf_lcd_pclk at offset 0x8E8

Bit 6 is the slew rate either fast or slow.

If we set the bit to 1 for slow slew rate, the behavior is NOT changing. Can someone confirm that this bit can be set and will have an effect on the slew rate of PCLK?

Thanks!

--Gunter