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AM5726: DDR3 ECC issue

Alberto Soattin
Genius 16905 points
Part Number: AM5726

Hi Support,

my customer is facing issues in adopting DDR3 with ECC with AM5726.

In particular, they generate all four pinmux files, they use the ‘BOARD=evmAM572x’ make option so all custom modifications are done for evmAM572x specific sources.

They have successfully built and tested SBL loaded from SDMMC and performed  a DRAM size detection and memtest. But when they enable ECC (they re-used code from idkAM572x sources) the SBL crashes on ‘Board_init(boardCfg)’ function call with ‘BOARD_INIT_DDR_ECC’ flag enabled (not used JTAG debugger to find the specific failing code position yet).

Can you help me finding out the root of this issue? I have sources in case of need.

Thanks in advance,

regards,

Alberto

 

  • 0
    TI__Guru**** 393215 points
    Alberto,

    What software is this? Is the customer aware of Errata i922?
  • 0 in reply to Biser Gatchev-XID
    TI__Genius 16905 points
    Biser,

    customer is using just bare metal code with CSL and DRV libraries from the TI PDK packages.
    Could you explain or suggest a reference regarding to the quanta* writes and EMIF regions partitioning?
    I am not familiar with that stuff yet.

    Thanks and regards,
    Alberto
  • 0 in reply to Alberto Soattin
    TI__Guru**** 393215 points
    I have asked the RTOS team to comment. They will continue from here.
  • 0 in reply to Alberto Soattin
    TI__Guru** 116170 points

    Alberto,

    If customer  has DDR ECC requirement in their product then we recommend that they consider looking at AM574x devices where we have fixed the errata in question. If you need information about AM574x launch date then please contact BU for more information.

    Basically the errata i922 indicates that EMIF ECC mechanism was found to operate correctly only when initiator of the read/write transaction used data sizes that equaled to total EMIF data lines used to interface with DDR. For eg if EMIF is configured for 32 bit DDR access, 32 bit data read/writes are quanta access and 8 bit and 16 bit access is a sub quanta access. The ECC mechanism on AM5726 works only when EMIF controller reads/writes 32 bit data (quanta size) to the DDR memory location that is multiple of 4 bytes (quanta aligned). IF any of the initiators write 8 bit or 16 bit  data he ECC mechanism would fail. Similarly, for 16 bit DDR configuration 16 bit data is quanta size and address location multiple of 2 bytes is quanta aligned.

    This bug was fixed in the AM574x by adding a read modify write feature on the EMIF lines for sub quanta accesses. This means that when the initiator tries to read/write data that is less than quanta size, the EMIF controller has a mechanism to read the remaining  bits from the DDR location, modify the data and then write it back to the external DDR memory as though it is a quanta sized data so that the ECC generation and read back is accurately generated in HW.

    Let me know if I have not sufficiently explained the issue and the fix and I will loop in a system/design expert to add more insight into this issue.

    From software perspective, we  have already integrated the DDR ECC feature into Processor SDK RTOS release 4.2 in the bootloader, board library and CSL examples. The feature is targeted to be supported in the 1Q2018 release that would include full support for AM574x platform.

    Reference to current software examples:

    • Bootloader : <PDK_INSTALL_PATH>\packages\ti\boot\sbl\board\idkAM574x
    • Board library support: <PDK_INSTALL_PATH>\packages\ti\board\src\idkAM574x
    • CSL example location in PDK: <PDK_INSTALL_PATH>\packages\ti\csl\example\ecc\ecc_test_app

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    TI__Genius 16905 points
    Rahul,

    thanks for your comprehensive feedback.
    I see the issues are solved for family AM574x but my customer already decided for AM572x. Can you kindly provide info on possible resolution of the issue also for this family?
    thanks and regards,
    Alberto
  • 0 in reply to Alberto Soattin
    TI__Guru** 116170 points
    Alberto,

    We are not supporting DDR ECC feature on AM572x due to this errata. There are many initiators on this device who can initiate a DDR transactions so it is not feasible for software implementation to guarantee that all access to external memory will be quanta sized and quanta aligned without considerable SW redesign. AM574x is pin to pin compatible with the AM5726 device. If DDR ECC is a product requirement, we strongly recommend switching to AM574x.

    If you or your customers still has concerns about this then, I would recommend taking this offline so we can have the right product marketing and system folks comment on risks of implementing the design on AM572x given this errata.

    Regards,
    Rahul