RTOS/PROCESSOR-SDK-AM335X: PRU access to SDRAM

Ok I solved it by setting in the cfg file MMU to sherable. You need to mark it so ARM wont block the PRU access. I also add this code into cfg:

// For Cortex-A8
var Cache = xdc.useModule('ti.sysbios.family.arm.a8.Cache');

var Mmu = xdc.useModule('ti.sysbios.family.arm.a8.Mmu');

// Enable the cache
Cache.enableCache = true;

// Enable the MMU (Required for L1/L2 data caching)
Mmu.enableMMU = true;

// descriptor attribute structure for marking the memory region
// as normal cacheable memory (write-back and write-allocate)
var attrs = {
type: Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
tex: 0x1,
bufferable: true, // bufferable
cacheable: true, // cacheable
shareable : true, <--------------------------------------------------------------------- U NEED TO ADD THIS THING
};

// Set the descriptor for each entry in the address range
for (var i=0x80000000; i < 0x90000000; i = i + 0x00100000) {
// Each 'SECTION' descriptor entry spans a 1MB address range
Mmu.setFirstLevelDescMeta(i, i, attrs);
}

var memmap = Program.cpu.memoryMap;
var DDR = null;

// Find DDR in memory map
for (var i=0; i < memmap.length; i++) {
if (memmap[i].name == "DDR") {
DDR = memmap[i];
}
}

// Place the MMU table in the DDR memory segment if it exists
if (DDR != null) {
var sectionName = "ti.sysbios.family.arm.a8.mmuTableSection";
Program.sectMap[sectionName] = new Program.SectionSpec();
Program.sectMap[sectionName].type = "NOLOAD"; // NOINIT for TI Tools
Program.sectMap[sectionName].loadSegment = "DDR";
}
else {
print("No DDR memory segment was found");
}


IMPORTANT TO REMEMBER ABOUT "shareable: true"

rafal,

Thanks for sharing your finding! This can be associated with the thread - e2e.ti.com/.../2420346

for reference.

Regards,
Garrett