TMS320C6678: L2 cache/ram memory access latency

Sung-IL,

On the latency to access another core's L2, it will be similar to DDR RAM situation, as Core0 has to first go out to MSMC->TeraNet->Core1_L2, as shown in Figure 1 of the same document. For example, if Core1 L2 is configured as SL3 to Core0, it may be ~100 CPU cycles with burst write when both Core0 caches miss.

On the burst write difference between DDR-RAM SL2 vs. SL3 - SL3 mode, cache lines with victim in L2 are to be read back and merged, that's why you see a large number of 115.5 cycles. In SL2 mode, the L2 cache is disabled, so the L1D cache miss is passed directly to DDR. In this case, since L1D does not write allocate (it does not allocate a cache line), therefore, there is no read back and merging to L1 cache lines, that's why you see the burst write to DDRRAM-SL2 show no cycle difference.

let me know if this clear, or you need more precise cycle estimates for L2 access from another core. It is only practical in very limited software design to use neighbor's L2.

Jian