EMIF CLOCK on C5504.

Hi:
On page 90 of SPRUGL6A it is stated that if the EDIV bit (bit 0) of the register ECDR is 0 then the EMIF operates at half the peripheral clock rate and if 1 it operates at the same rate as the peripheral clock. However, figure 1-2 on page 15 of SPRUGU6 indicates EDIV controlling the SDRAM clock. The figure also indicates that the EMIF clock is the sameas the DSP system clock and it has no divider. Could you please help resolve this?
Thanks a lot.
Cheers,
Mushtaq