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TMS320C5505: C5505 strapping discrepancies

William Tolli
Prodigy 40 points
Part Number: TMS320C5505


Hi All,

I have some questions about the hardware implementation of the C5505.

1) The following two documents show discrepancies between the connections for pins J10 and J11.  In the first document (C5505 datasheet) these pins are supposed to be strapped high.  In the schematic for the USB devkit, these pins are left as NCs.  We have been using the USB devkit to develop our application for several months and have had no problems with that hardware.  Now we are laying out our PCB and this detail has come up.  What are we supposed to do with these pins??

www.ti.com/.../tms320c5505.pdf

support.spectrumdigital.com/.../usbstk5505_Schematics_revb.pdf

2) On the same pages as the above links; The pin D13 is supposed to be tied to VSS in the datasheet and in the USB devkit, it is pulled-up.  Given the description of this pin's function in the USB devkit schematic, it seems like the correct connection of this pin is to pull-up.  Which is correct??

3) In the link below; Pin D12 is labeled as DSP_LDO_EN.  Per the note, I am not using the DSP_LDO output pin to provide CVDD.  However, there is also an analog LDO inside the device that is powering the PLL and analog circuits.  Will this pin D12 affect the analog LDO operation?  We do not need the RTC only mode of operation for our application.

www.ti.com/.../tms320c5505.pdf

4) The C5505 device has ROM inside which stores the default boot-loader for searching the various memory ports for a boot file.  Is there any way to get devices with a modified boot-loader installed?  Specifically, I am looking to get the encryption code hard-coded into the boot-loader so that it is not transferred from the memory device to the processor over the databus.  If this is possible, how many parts would we have to buy to be able to get the boot-loader customized?

Thanks,

-William

  • 0
    TI__Guru 65405 points
    The team is notified. They will post their feedback directly here.

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    Prodigy 40 points
    Hello Tsvetolin,
    When can I expect a response to this issue? The first 3 questions are the most immediately pressing. The last question can be figured out later as we approach production.
  • 0 in reply to William Tolli
    TI__Mastermind 30140 points

    Hi William,

    When in doubt, trust the datasheet, not the schematics.

    1)
    J10 - RSV1 - tie directly to CVDD
    J11 - RSV2 - tie directly to CVDD
    These two pins are reserved for device test and programming. Most of the EVMs do tie these to CVDD (C5505, C5515, C5517). The C5505 eZdsp Rev D has them tied to CVDD. But I see that the C5505 EVM (bigger board) does leave these pins floating. All the boards operate.
    I recommend to tie them directly to CVDD per the datasheet.

    2)
    D13 - RSV16 - tie directly to VSS
    This is the former DSP_LDO_V pin - it was used to select DSP_LDO voltage: 1.05V or 1.3V.
    Since PG2.0, it is no longer used and the IO buffer's Y port goes nowhere, but to avoid power consumption, this buffer's input must not be left floating.
    Recommend to tie directly to VSS per the datasheet.

    3)
    D12 - DSP_LDO_EN - tie to VSS or LDOI depending on if DSP_LDO is used to supply CVDD.
     - VSS (0): DSP_LDO is enabled, also internal POR monitors DSP_LDO and holds reset until DSP_LDO crosses ~1V (internal POR is ANDed with RESET pin)
     - LDOI (1): DSP_LDO is disabled
    Usage of this pin depends on if you have CVDD supplied by DSP_LDO

    4)
    I have asked about the availability of encryption on C5505 or custom ROM code, but I do not expect TI to support this with any min order quantity. Will follow up here with more.

    Have you seen the C5505 schematic review checklist? processors.wiki.ti.com/.../35_Schematic_Checklist

    Some common mistakes I have seen: do not supply CVDDRTC with any on-chip LDO, if using USB follow USB power sequencing, terminate all input pins to avoid power consumption caused by oscillating inputs, utilize internal pull-up/down resistors to save BOM cost, on-chip LDOs ramp much up slower than off-chip LDOs, It is better to use slave mode for I2S (more precise audio clocks), route JTAG on production (or alpha/beta) boards for easier debugging, bring out XF pin and CLKOUT to test points...

    Let me know if you have any more questions.

    Hope this helps,
    Mark

  • 0 in reply to Mark M
    TI__Guru* 84475 points
    Hi William
    I confirm on #4 we are no longer supporting any custom ROM code opportunity on c55x family.
    For secure boot support , you would need to look at newer ISAs in our c6000 or Sitara family.


    Regards
    Mukul