• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 99 subscribers
  • Views 1071 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Linux/OMAP-L138: McASP ACLKR output clock

Tom Riddle83
Intellectual 660 points

Part Number: OMAP-L138

Tool/software: Linux

Hi,

I am working with an OMAP-L138 and have configured it's McASP Rx clock generation circuit to output a bit and frame clock, but have been unable to observe the expected signals. Our setup...

There is an external clock source of 24.576Mhz at the AHCLKR pin. The PFUNC reg is 0x0 so all functions of the McASP are enabled. The PDIR reg is 0xb400.1000 indicating AHCLKR and AHCLKR as inputs and AFSR, ACLKR, AFSX and  ACLKX as outputs.   The GBLCTL is 0x1f1f indicating everything is out of reset.. The  AHCLKRCTL is 0x0 so the HCLKRM is set for the external clock source. The ACLKRCTL reg is 0x1 so a simple div by 2.

We see no output clock or signal activity on the ACLKR pin, according to 25.0.21.2 of the user's manual with these settings we should see a free running clock... correct? Or has something been overlooked?

Thanks in advance, Tom

  • 0
    TI__Guru 65405 points
    The team is notified. They will post their feedback directly here.

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    Intellectual 660 points

    Thank you. Here is some updated information

    We've been successful in generating an Rx frame clock (AFSR) but we cannot observe the expected output clock (ACLKR). So seeing the AFSR output confirms a number of things, since this is driven off of the RCLK. The regs of interest are listed below with their values

    AHCLKRCTL = 0x0
    ACLKRCTL = 0xaf
    AHCLKXCTL = 0x0
    ACLKXCTL = 0xef

    tracing back ACLKXCTL.6 = 1, which is ASYNC operation, thus RCLK will come from the Rx clock generator.
    next ACLKRCTL.5 = 1 CLKRM = 1, and AHCLKRCTL.15 = 0 HCLKRM = 0 so our external input clock on AHCLKR pin is verified.

    So now we look at the ACLKR pin itself

    The McASP PFUNC reg = 0x0, all McASP signals are enabled. Then

    MCASP_PDIR = 0xb4008000

    Which has our external sysclk driving both the inputs AHCLKR & AHCLKX. The rest are outputs.

  • 0 in reply to Tom Riddle83
    TI__Mastermind 30601 points

    Hi Tom,

    I checked your register settings, and the second post settings pass my inspection. See tips below...

    ----

    Check the Pin Multiplexing Control Registers (PINMUX0-PINMUX19)

    Ensure PINMUX0.[3:0] = 1h (Selects Function ACLKR)

    Refer to TRM Table 11-23. Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions

    SPRUH77C - http://www.ti.com/lit/pdf/spruh77

    ----

    Ensure you have exactly followed the McASP Sequence in TRM 25.0.21.1.2 Transmit/Receive Section Initialization

    - Specifies exact order to configure all McASP registers and GBLCTL register bits

    - Final step is to release frame sync generators from reset

    - It is important to read back GBLCTL register during init sequence

    ----

    What is the value of ACLKRCTL? You have conflicting values in each post.

    ACLKRCTL = 0x1 - div by 2:

           - BAD If 0x1, then ACLKRCTL.5 = 0, External receive clock source from ACLKR pin.

           - and  ACLKRCTL.[4:0] = 0x1 (div by 2)

    ACLKRCTL = 0xaf - ACLKRCTL.5 = 1 CLKRM = 1, and AHCLKRCTL.15 = 0 HCLKRM = 0 so our external input clock on AHCLKR pin is verified:

           - OK If 0xaf, then ACLKRCTL.5 = 1, Internal receive clock source from output of programmable bit clock divider

           - and  ACLKRCTL.[4:0] = 0xF (div by 16)

    ----

    Once you get past this clocking issue, check this wiki for more McASP tips: http://processors.wiki.ti.com/index.php/McASP_Tips 

    =-=-=-=-

    Checking your register settings:

    No output clock or signal activity on the ACLKR pin

    OK: PFUNC reg is 0x0

    OK: PDIR reg is 0xb400.1000 - AHCLKR and AHCLKR as inputs and AFSR, ACLKR, AFSX and  ACLKX as outputs

    CONFIRM SEQUENCE: GBLCTL is 0x1f1f indicating everything is out of reset

    OK: AHCLKRCTL is 0x0 so the HCLKRM is set for the external clock source

    BAD: ACLKRCTL reg is 0x1 so a simple div by 2 - ACLKRCTL.5 = 0, External receive clock source from ACLKR pin (should be 1)

    ----

    Rx frame clock (AFSR) works

    Still no ACLKR

    OK AHCLKRCTL = 0x0

    OK ACLKRCTL = 0xaf - ACLKRCTL.5 = 1 CLKRM = 1, and AHCLKRCTL.15 = 0 HCLKRM = 0 so our external input clock on AHCLKR pin is verified

    OK AHCLKXCTL = 0x0

    OK ACLKXCTL = 0xef - ACLKXCTL.6 = 1, which is ASYNC operation, RCLK will come from the Rx clock generator

    OK McASP PFUNC reg = 0x0, all McASP signals are enabled

    OK MCASP_PDIR = 0xb4008000 - external sysclk driving both the inputs AHCLKR & AHCLKX, rest outputs

    ----

    Hope this helps,
    Mark

  • 0 in reply to Mark M
    Intellectual 660 points
    Mark, Thanks for the detailed explanation. I was able to get the ACLKR output going, indeed it was related to the PINMUX0 settings. But I do appreciate the extra explanation as it cleared up some additional questions I had. Regs, Tom