Linux/DRA750: The problem to use TPS65917 PMIC on DRA752 CPU

Ren Bowei

Intellectual 650 points

Part Number: DRA750
Other Parts Discussed in Thread: DRA752

Tool/software: Linux

Dear Sir,

We use TPS65917 PMIC and DRA752 CPU on our customized board.

We cannot bring up successfully and no any message output on the console.

So we tried to add some debug message in MLO, we found out it should be PMIC issue.

The error message as below:

U-Boot SPL 2014.07 (Sep 05 2017 - 17:07:20)
DRA752-GP ES2.0
before do_io_settings
before prcm_init
        |-before enable_basic_clocks
Enable clock domain - 4a009700
Enable clock domain - 4a009300
Enable clock domain - 4a008b00
Enable clock domain - 4a008d00
Enable clock domain - 4a0093c0
Enable clock domain - 4a008700
Enable clock module - 4a008728
Enable clock module - 4a008b30
Enable clock module - 4a008b38
Enable clock module - 4a008d20
Enable clock module - 4ae07838
Enable clock module - 4a009760
Enable clock module - 4a009768
Enable clock module - 4a009770
Enable clock module - 4a009778
Enable clock module - 4a009780
Enable clock module - 4a009810
Enable clock module - 4a009818
Enable clock module - 4a008778
Enable clock module - 4a008780
Enable clock module - 4ae07840
Enable clock module - 4a009328
Enable clock module - 4a009330
Enable clock module - 4a009738
Enable clock module - 4ae07830
Enable clock module - 4a009850
Enable clock module - 4a0097a0
Enable clock module - 4a0093d0
Enable clock module - 4a009838
Enable clock domain - 4a009700
Enable clock domain - 4a009300
Enable clock domain - 4a008b00
Enable clock domain - 4a008d00
Enable clock domain - 4a0093c0
Enable clock domain - 4a008700
        |-before timer_init
        |-before scale_vcores
                |-before vcores->core
optimize_vcore_voltage:efuse 0x4a0025f4 bits=16 Vnom=1030, using efuse value 1045
                |-before core
do_scale_vcore: volt - 1045 offset_code - 0x3d

The boot flow to "do_scale_vcore: volt - 1045 offset_code - 0x3d", it will reboot.

Could you give me some directions to debug further? maybe we need to modify efuse voltage in MLO?

Thanks for your support in advance.

Best Regards,

Bowei

over 8 years ago

0 Yordan Kamenov over 8 years ago

TI__Mastermind 42515 points

Hi,

I have forwarded your question to power management expert.

Regards,
Yordan

0 Ren Bowei over 8 years ago in reply to Yordan Kamenov

Intellectual 650 points

Dear,

Thanks for your support.

Update the status from our side, as I know, DDR and PMIC have the formal combination. Right?

For example, DRA752 + TPS659038 are formal combination, but DRA752 + TPS65917 are not.

So the boot flow hanged on checking PMIC voltage (vcore). After modifying MLO source code, the boot flow will go.

We would like to confirm with you, this way of modification is correct or not. Please refer the fragment of source code what we modified.

Modified the file <the directory of source code>/board-support/u-boot/arch/arm/cpu/armv7/omap5/hw_data.c
We replaced "omap_vcores = &dra752_volts;" with "//*omap_vcores = &dra722_volts;".

====================================================================
...
void __weak hw_data_init(void)
{
	u32 omap_rev = omap_revision();

	switch (omap_rev) {

	case OMAP5430_ES1_0:
	case OMAP5432_ES1_0:
	*prcm = &omap5_es1_prcm;
	*dplls_data = &omap5_dplls_es1;
	*omap_vcores = &omap5430_volts;
	*ctrl = &omap5_ctrl;
	break;

	case OMAP5430_ES2_0:
	case OMAP5432_ES2_0:
	*prcm = &omap5_es2_prcm;
	*dplls_data = &omap5_dplls_es2;
	*omap_vcores = &omap5430_volts_es2;
	*ctrl = &omap5_ctrl;
	break;

	case DRA752_ES1_0:
	case DRA752_ES1_1:
	case DRA752_ES2_0:
	*prcm = &dra7xx_prcm;
	*dplls_data = &dra7xx_dplls;
	//*omap_vcores = &dra752_volts;
	*omap_vcores = &dra722_volts;
	*ctrl = &dra7xx_ctrl;
	break;

	case DRA722_ES1_0:
	*prcm = &dra7xx_prcm;
	*dplls_data = &dra72x_dplls;
	*omap_vcores = &dra722_volts;
	*ctrl = &dra7xx_ctrl;
	break;

	default:
		printf("\n INVALID OMAP REVISION ");
	}
}
...
====================================================================

I am not sure is this method feasible. Could you help me to double check?

Thank you very much!

Best Regards,

Bowei Ren

0 Ren Bowei over 8 years ago in reply to Ren Bowei

Intellectual 650 points

Dear Sir,

Do you have any update for this question?

Best Regards,
Bowei

0 Ravikumar Kattekola over 8 years ago in reply to Ren Bowei

TI__Expert 4230 points

Hi Bowei,
The method used is wrong. Voltage settings are based on Data Manual so you should use what's applicable for the device in use.

Regards,
RK

0 Ravikumar Kattekola over 8 years ago in reply to Ravikumar Kattekola

TI__Expert 4230 points

Also,  looking at the code flow, the settings done in hw_data_init() will be over-written by vcores_update()

void early_system_init(void)  
{                             
        init_omap_revision(); 
        hw_data_init();       
                              
#ifdef CONFIG_SPL_BUILD       
        if (warm_reset())     
                force_emif_self_refresh();
#endif                                    
        watchdog_init();                  
        set_mux_conf_regs();              
#ifdef CONFIG_SPL_BUILD                   
        srcomp_enable();                  
        do_io_settings();                 
#endif                                    
        setup_early_clocks();             
        do_board_detect();                
        vcores_update();                  
        prcm_init();                      
}

Regards,
RK

0 Ravikumar Kattekola over 8 years ago in reply to Ravikumar Kattekola

TI__Expert 4230 points

Hi Bowei,

Efuse voltages are based on device characteristics not PMIC and have nothing to do with PMIC itself or the connections.

The difference is the SMPS register addresses are different between tps659038 and tps65917.

Here's what you need to do:

1. Check your vdd connection to pmic smps

mpu -> smps1??

2. Update dra752_volts() data structure in board/ti/dra7xx/evm.c with correct addresses,

for example if vdd_mpu is connected to SMPS1 then update

.mpu.addr = TPS659038_REG_ADDR_SMPS12,

.mpu.addr = TPS65917_REG_ADDR_SMPS1,

similarly do for all vdds (vdd_core, gpu, eve, iva etc).

3. also check if i2c slave address for the PMIC is same as EVM, on EVm it's 0x58,

otherwise update

pmic_data tps659038 {..i2c_slave_addr = < i2c slave address>} , arch/arm/cpu/armv7/omap5/hw_data.c

Let me know if this fixes your problem.

Regards,

Processors

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Linux/DRA750: The problem to use TPS65917 PMIC on DRA752 CPU