PROCESSOR-SDK-AM335X: SPI receive not working

David Schmittwilken

I started to implement SPI für SPI1 and used SPI0 Flash Example as a base, but I can't get it working. I seems that I even don't receive any data. I enabled all Clocks and configured the Pinmux for all need Pins. I want to recieve data only. The SPI receive register "MCSPI_RX0" is always zero and interrupt is never triggered. In the following you can see my code. Am I missing anything?

Update1: After removing the line where I activated the RX FIFO I now have the correct data in MCSPI_RX0 register, but the my receive interrupt is not triggered. Now I try using the FIFO register.

Update2: Interrupt is now triggered in none fifo mode. I missed enabling master interrupt (IntMasterIRQEnable).

#define PINMODE3 3

McSPI1ModuleClkConfig();

McSPIReset(MCSPISLV_MCSPI_REGS);
MCSPISysConfigSetup(MCSPISLV_MCSPI_REGS, MCSPI_CLOCKS_OCP_ON_FUNC_ON,
                                    MCSPI_SIDLEMODE_NO, MCSPI_WAKEUP_DISABLE,
                                    MCSPI_AUTOIDLE_OFF);
McSPICSEnable(MCSPISLV_MCSPI_REGS);
McSPISlaveModeEnable(MCSPISLV_MCSPI_REGS);
MCSPIPinDirSet(SOC_SPI_1_REGS, MCSPI_RX_ONLY_MODE, MCSPI_DATA_LINE_COMM_MODE_7, 0);
MCSPIMultiChModeEnable(SOC_SPI_1_REGS);
McSPIClkConfig(SOC_SPI_1_REGS, MCSPI_IN_CLK, MCSPI_OUT_FREQ,
               MCSPI_CH_NUM, MCSPI_CLK_MODE_0);

McSPIWordLengthSet(MCSPISLV_MCSPI_REGS, MCSPI_WORD_LENGTH(8), MCSPI_CH_ZERO);

McSPICSPolarityConfig(MCSPISLV_MCSPI_REGS, MCSPI_CS_POL_LOW, MCSPI_CH_ZERO);

McSPIIntEnable(MCSPISLV_MCSPI_REGS, MCSPI_INT_RX_FULL(MCSPI_CH_ZERO));

McSPIRxFIFOConfig(MCSPISLV_MCSPI_REGS, MCSPI_RX_FIFO_ENABLE, MCSPI_CH_ZERO);

    /* Initializing the ARM Interrupt Controller. */
    IntAINTCInit();

    /* Registering  interrupt.  */
    IntRegister(SYS_INT_SPI1INT, SPIReceiveIsr);

    /* Setting the priority for interrupt in AINTC. */
    IntPrioritySet(SYS_INT_SPI1INT, 0, AINTC_HOSTINT_ROUTE_IRQ);

    /* Enabling the  interrupt in AINTC. */
    IntSystemEnable(SYS_INT_SPI1INT);

McSPIChannelEnable(MCSPISLV_MCSPI_REGS, MCSPI_CH_ZERO);

McSPIReceiveData(MCSPISLV_MCSPI_REGS, MCSPI_CH_ZERO);
}

int McSPI1PinMuxSetup()
{
                                HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI1_SCLK) =  CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL | CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE | PINMODE3;
                                HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI1_D0) =  CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL | CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE | PINMODE3;
                                HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI1_D1) =  CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL | CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE | PINMODE3;
                                HWREG(SOC_CONTROL_REGS + CONTROL_CONF_SPI1_CS0) =  CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL | CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE | PINMODE3;
}

void McSPI1ModuleClkConfig(void)
{
    HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) =
                             CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
     CM_PER_L3S_CLKSTCTRL_CLKTRCTRL) != CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP);

    HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) =
                             CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
     CM_PER_L3_CLKSTCTRL_CLKTRCTRL) != CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP);

    HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) =
                             CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) &
                               CM_PER_L3_INSTR_CLKCTRL_MODULEMODE) !=
                                   CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE);

    HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) =
                             CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) &
        CM_PER_L3_CLKCTRL_MODULEMODE) != CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE);

    HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) =
                             CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
                              CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL) !=
                                CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP);

    HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) =
                             CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &
                             CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL) !=
                               CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP);

    HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) =
                             CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) &
      CM_PER_L4LS_CLKCTRL_MODULEMODE) != CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE);

    HWREG(SOC_CM_PER_REGS + CM_PER_SPI1_CLKCTRL) &= ~CM_PER_SPI1_CLKCTRL_MODULEMODE;

    HWREG(SOC_CM_PER_REGS + CM_PER_SPI1_CLKCTRL) |=
                             CM_PER_SPI1_CLKCTRL_MODULEMODE_ENABLE;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_SPI1_CLKCTRL) &
      CM_PER_SPI1_CLKCTRL_MODULEMODE) != CM_PER_SPI1_CLKCTRL_MODULEMODE_ENABLE);


    while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
            CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK));

    while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
            CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK));

    while(!(HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
           (CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK |
            CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK)));

    while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &
           (CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK |
            CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_SPI_GCLK)));

}

Resulting Registers:

McSPI1	McSPI1 Registers	
	MCSPI_REVISION	0x40300A0B	The McSPI system configuration register (MCSPI_REVISION) allows control of various parameters of the module interface. It is not sensitive to software reset. [Memory Mapped]	
	MCSPI_SYSCONFIG	0x00000308	The McSPI system configuration register (MCSPI_SYSCONFIG) allows control of various parameters of the module interface. It is not sensitive to software reset. [Memory Mapped]	
	MCSPI_SYSSTATUS	0x00000001	The McSPI system status register (MCSPI_SYSSTATUS) provides status information about the module excluding the interrupt status information. [Memory Mapped]	
	MCSPI_IRQSTATUS	0x00010001	The McSPI interrupt status register (MCSPI_IRQSTATUS) regroups all the status of the module internal events that can generate an interrupt. [Memory Mapped]	
	MCSPI_IRQENABLE	0x00000004	This McSPI interrupt enable register (MCSPI_IRQENABLE) enables/disables the module internal sources of interrupt, on an event-by-event basis. [Memory Mapped]	
	MCSPI_SYST	0x00000000	This McSPI system register (MCSPI_SYST) is used to configure the system interconnect either internally to the peripheral bus or externally to the device I/O pads, when the module is configured in the system test (SYSTEST) mode.  [Memory Mapped]	
	MCSPI_MODULCTRL	0x00000004	This McSPI module control register (MCSPI_MODULCTRL) is used to configure the serial port interface. [Memory Mapped]	
	MCSPI_CH0CONF	0x100713C4	The McSPI channel 0 configuration register (MCSPI_CH0CONF) is used to configure channel 0. [Memory Mapped]	
	MCSPI_CH0STAT	0x00000022	The McSPI channel 0 status register (MCSPI_CH0STAT) provides status information about the McSPI channel 0 FIFO transmit buffer register (MCSPI_TX0) and the McSPI channel 0 FIFO receive buffer register (MCSPI_RX0) of channel 0.  [Memory Mapped]	
	MCSPI_CH0CTRL	0x00000001	Memory Mapped	
	MCSPI_TX0	0x00000000	Memory Mapped	
	MCSPI_RX0	0x00000000	The McSPI channel 0 FIFO receive buffer register (MCSPI_RX0) contains a single McSPI word received through the serial link. Little endian host access SPI 8 bit word on 0; big endian host accesses on 3h.  [Memory Mapped]	
	MCSPI_CH1CONF	0x00060000	The McSPI channel 1 configuration register (MCSPI_CH1CONF) is used to configure channel 1. [Memory Mapped]	
	MCSPI_CH1STAT	0x00000000	The McSPI channel 1 status register (MCSPI_CH1STAT) provides status information about the McSPI channel 1 FIFO transmit buffer register (MCSPI_TX1) and the McSPI channel 1 FIFO receive buffer register (MCSPI_RX1) of channel 1.  [Memory Mapped]	
	MCSPI_CH1CTRL	0x00000000	Memory Mapped	
	MCSPI_TX1	0x00000000	Memory Mapped	
	MCSPI_RX1	0x00000000	The McSPI channel 1 FIFO receive buffer register (MCSPI_RX1) contains a single McSPI word received through the serial link. Little endian host access SPI 8 bit word on 0; big endian host accesses on 3h.  [Memory Mapped]	
	MCSPI_CH2CONF	0x00060000	The McSPI channel 2 configuration register (MCSPI_CH2CONF) is used to configure channel 2. [Memory Mapped]	
	MCSPI_CH2STAT	0x00000000	The McSPI channel 2 status register (MCSPI_CH2STAT) provides status information about the McSPI channel 2 FIFO transmit buffer register (MCSPI_TX2) and the McSPI channel 2 FIFO receive buffer register (MCSPI_RX2) of channel 2.  [Memory Mapped]	
	MCSPI_CH2CTRL	0x00000000	Memory Mapped	
	MCSPI_TX2	0x00000000	Memory Mapped	
	MCSPI_RX2	0x00000000	The McSPI channel 2 FIFO receive buffer register (MCSPI_RX2) contains a single McSPI word received through the serial link. Little endian host access SPI 8 bit word on 0; big endian host accesses on 3h.  [Memory Mapped]	
	MCSPI_CH3CONF	0x00060000	The McSPI channel 3 configuration register (MCSPI_CH3CONF) is used to configure channel 3. [Memory Mapped]	
	MCSPI_CH3STAT	0x00000000	The McSPI channel 3 status register (MCSPI_CH3STAT) provides status information about the McSPI channel 3 FIFO transmit buffer register (MCSPI_TX3) and the McSPI channel 3 FIFO receive buffer register (MCSPI_RX3) of channel 3.  [Memory Mapped]	
	MCSPI_CH3CTRL	0x00000000	Memory Mapped	
	MCSPI_TX3	0x00000000	Memory Mapped	
	MCSPI_RX3	0x00000000	The McSPI channel 3 FIFO receive buffer register (MCSPI_RX3) contains a single McSPI word received through the serial link. Little endian host access SPI 8 bit word on 0; big endian host accesses on 3h.  [Memory Mapped]	
	MCSPI_XFERLEVEL	0x00000000	The McSPI transfer levels register (MCSPI_XFERLEVEL) provides the transfer levels needed while using the FIFO buffer during transfer. [Memory Mapped]	
	MCSPI_DAFTX	0x00000000	The McSPI DMA address aligned FIFO transmitter register (MCSPI_DAFTX) contains the SPI words to transmit on the serial link when FIFO is used and the DMA address is aligned on 256 bit. This register is an image of one of the MCSPI_TX(i) registers corresponding to the channel which have its FIFO enabled. The SPI words are transferred with MSB first. See Chapter Access to data registers for the list of supported accesses. [Memory Mapped]	
	MCSPI_DAFRX	0x00000000	The McSPI DMA address aligned FIFO receiver register (MCSPI_DAFRX) contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit. This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled.  [Memory Mapped]	

CPSR	0x6000019F	Stores the status of interrupt enables and critical processor status signals [Core]	
	N	0	Stores bit 31 of the result of the instruction. In other words stores the sign of the number	
	Z	1	Is set to 1 if the result of the operation is zero else stays 0	
	C	1	Stores the value of the carry bit if it occurred in an addition or the borrow bit in a subtraction. In a shift stores the last bit shifted out.	
	V	0	Set to 1 if an overflow occurred 	
	Q	0	Indicates whether an overflow or a saturation occurred in the enhanced DSP instructions	
	IT_1_0	00	IT state bits.	
	J	0	Java State Bit.	
	Reserved	0000	Reserved.	
	GE	0000	Greater than or equal bits	
	IT_7_2	000000	IT state bits	
	E	0	If set, data memory is interpreted as big-endian. If cleared data memory is interpreted as little-endian.	
	A	1	If set, any asynchronous abort is held pending until this bit is cleared.	
	I	1	If set, IRQ is disabled. If cleared IRQ is allowed	
	F	0	If set, FIQ is disabled. If cleared FIQ is allowed	
	T	0	If set ARM is in Thumb mode	
	M	11111	Mode of ARM	

CM_PER_SPI1_CLKCTRL	0x00000002	This register manages the SPI1 clocks. [Memory Mapped]	
	Reserved1	00000000000000	Reserved	
	IDLEST	00 - Func	Module idle status.	
	Reserved	00000000000000	Reserved	
	MODULEMODE	10 - ENABLE	Control the way mandatory clocks are managed.	

CM_PER_L4LS_CLKSTCTRL	0x1A006102	This register enables the domain power state transition. It controls the SW supervised clock domain state transition between ON-PER and ON-INPER states. It also hold one status bit per clock input of the domain. [Memory Mapped]	
	Reserved5	000	Reserved	
	CLKACTIVITY_TIMER6_GCLK	1 - Act	This field indicates the state of the TIMER6 CLKTIMER  clock in the domain.	
	CLKACTIVITY_TIMER5_GCLK	1 - Act	This field indicates the state of the TIMER5 CLKTIMER  clock in the domain.	
	Reserved6	0	Reserved.	
	CLKACTIVITY_SPI_GCLK	1 - Act	This field indicates the state of the SPI_GCLK  clock in the domain.	
	CLKACTIVITY_I2C_FCLK	0 - Inact	This field indicates the state of the I2C _FCLK  clock in the domain.	
	Reserved4	0	Reserved	
	Reserved7	0	Reserved.	
	CLKACTIVITY_GPIO_3_GDBCLK	0 - Inact	This field indicates the state of the GPIO3_GDBCLK  clock in the domain.	
	CLKACTIVITY_GPIO_2_GDBCLK	0 - Inact	This field indicates the state of the GPIO2_ GDBCLK clock in the domain.	
	CLKACTIVITY_GPIO_1_GDBCLK	0 - Inact	This field indicates the state of the GPIO1_GDBCLK  clock in the domain.	
	Reserved8	0	Reserved.	
	CLKACTIVITY_LCDC_GCLK	0 - Inact	This field indicates the state of the LCD clock in the domain.	
	CLKACTIVITY_TIMER4_GCLK	0 - Inact	This field indicates the state of the TIMER4 CLKTIMER  clock in the domain.	
	CLKACTIVITY_TIMER3_GCLK	0 - Inact	This field indicates the state of the TIMER3 CLKTIMER  clock in the domain.	
	CLKACTIVITY_TIMER2_GCLK	1 - Act	This field indicates the state of the TIMER2 CLKTIMER  clock in the domain.	
	CLKACTIVITY_TIMER7_GCLK	1 - Act	This field indicates the state of the TIMER7 CLKTIMER  clock in the domain.	
	Reserved3	0	Reserved	
	CLKACTIVITY_CAN_CLK	0 - Inact	This field indicates the state of the CAN_CLK clock in the domain.	
	CLKACTIVITY_UART_GFCLK	0 - Inact	This field indicates the state of the UART_GFCLK  clock in the domain.	
	Reserved2	0	Reserved	
	CLKACTIVITY_L4LS_GCLK	1 - Act	This field indicates the state of the L4LS_GCLK  clock in the domain.	
	Reserved	000000	Reserved	
	CLKTRCTRL	10 - SW_WKUP	Controls the clock state transition of the L4 SLOW clock domain in PER power domain.	

CM_PER_L3S_CLKSTCTRL	0x0000000A	This register  enables  the domain power state transition. It controls the SW supervised clock domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain. [Memory Mapped]	
	Reserved1	000000	Reserved	
	Reserved2	000000000000000	Reserved	
	Reserved4	0	Reserved	
	Reserved5	0	Reserved	
	Reserved3	0	Reserved	
	Reserved	000	Reserved	
	Reserved6	0	Reserved	
	CLKACTIVITY_L3S_GCLK	1 - Act	This field indicates the state of the  L3S_GCLK clock in the domain.	
	Reserved7	0	Reserved	
	CLKTRCTRL	10 - SW_WKUP	Controls the clock state transition of the L3 Slow clock domain.	

conf_mcasp0_aclkx	0x00000033	See the device datasheet for information on default pin mux configurations. Note that the device ROM may change the default pin mux for certain pins based on the SYSBOOT mode settings. [Memory Mapped]	
conf_mcasp0_fsx	0x00000033	See the device datasheet for information on default pin mux configurations. Note that the device ROM may change the default pin mux for certain pins based on the SYSBOOT mode settings. [Memory Mapped]	
conf_mcasp0_axr0	0x00000033	See the device datasheet for information on default pin mux configurations. Note that the device ROM may change the default pin mux for certain pins based on the SYSBOOT mode settings. [Memory Mapped]	
conf_mcasp0_ahclkr	0x00000033	See the device datasheet for information on default pin mux configurations. Note that the device ROM may change the default pin mux for certain pins based on the SYSBOOT mode settings. [Memory Mapped]	
conf_mcasp0_aclkr	0x00000027	See the device datasheet for information on default pin mux configurations. Note that the device ROM may change the default pin mux for certain pins based on the SYSBOOT mode settings. [Memory Mapped]	
conf_mcasp0_fsr	0x00000027	See the device datasheet for information on default pin mux configurations. Note that the device ROM may change the default pin mux for certain pins based on the SYSBOOT mode settings. [Memory Mapped]	
conf_mcasp0_axr1	0x00000027	See the device datasheet for information on default pin mux configurations. Note that the device ROM may change the default pin mux for certain pins based on the SYSBOOT mode settings. [Memory Mapped]	
conf_mcasp0_ahclkx	0x00000027	See the device datasheet for information on default pin mux configurations. Note that the device ROM may change the default pin mux for certain pins based on the SYSBOOT mode settings. [Memory Mapped]

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

What software is this?

0 David Schmittwilken over 8 years ago in reply to Biser Gatchev-XID

Intellectual 300 points

Software Version: pdk_am335x_1_0_9

I am using the CSL spi receive without fifo is working, but when I try using dma with fifo, my receivebuffer is filled with 0xFFFF. Any ideas?

Source code extract:

/* Include all the necessary header files */
#include "stdint.h"
#include "mcspi.h"
#include "hw_mcspi.h"
#include "edma_event.h"
#include "soc_AM335x.h"
#include "evmAM335x.h"
#include "interrupt.h"
#include "hw_types.h"

#include "error.h"
#include "edma.h"

/*****************************************************************************/
/*                      INTERNAL MACRO DEFINITIONS                           */
/*****************************************************************************/
//#define MCSPI_TX_EVENT                  (EDMA3_CHA_MCSPI0_CH0_TX)
//#define MCSPI_RX_EVENT                  (EDMA3_CHA_MCSPI0_CH0_RX)
#define MCSPI_TX_EVENT                  (EDMA3_CHA_MCSPI1_CH0_TX)
#define MCSPI_RX_EVENT                  (EDMA3_CHA_MCSPI1_CH0_RX)
//#define MCSPI_TX0_REG                   (0x48130138u)
#define MCSPI_TX0_REG                   (0x481A0138u)
//#define MCSPI_RX0_REG                   (0x4803013Cu)
#define MCSPI_RX0_REG                   (0x481A013Cu)
#define MCSPI_IN_CLK                    (48000000u)
#define MCSPI_OUT_FREQ                  (24000000u)
#define MCSPI_CH_NUM                    (0u)
#define EVT_QUEQUE_NUM                  (0u)
#define DUMMY_CH_NUM                    (5u)
#define MCSPISLV_MCSPI_REGS             SOC_SPI_1_REGS
#define MCSPI_CH_ZERO                           (0u)

#define FIFORX                          16
#define DATALENGTH                      32




#define MCSPI_SIDLEMODE_NO            ((uint32_t) MCSPI_SYSCONFIG_SIDLEMODE_NO \
                                       << MCSPI_SYSCONFIG_SIDLEMODE_SHIFT)
/*****************************************************************************/
/*                      LOCAL FUNCTION PROTOTYPES                            */
/*****************************************************************************/
static void McSpiTxEdmaParamSet(unsigned int tccNum, unsigned int chNum,
                                volatile unsigned char *buffer,
                                unsigned short buffLength);
static void McSpiRxEdmaParamSet(unsigned int tccNum, unsigned int chNum,
                                volatile unsigned char *buffer,
                                unsigned short buffLength,
                                unsigned int destBidxFlag);
static void CallBack(unsigned int tccNum, unsigned int status);
static void McSPITransfer(unsigned short length);
static void TxDummyPaRAMConfEnable(void);
static void Edma3ErrorHandlerIsr(void);
static void Edma3ComplHandlerIsr(void);
static void RequestEDMA3Channels(void);
static void EDMA3AINTCConfigure(void);
static void EDMA3Initialize(void);
static void McSPISetUp(void);

static void testSPIEdma();

/*****************************************************************************/
/*                         GLOBAL VARIABLES                                  */
/*****************************************************************************/
static void (*cb_Fxn[EDMA3_NUM_TCC])(unsigned int tcc, unsigned int status);

uint16_t rxBuffer[100] __attribute__ ((aligned (256)));

volatile unsigned char vrfyData[256];
volatile unsigned char flagTx = 0;
volatile unsigned char flagRx = 0;
static uint8_t myCount = 0;

/*****************************************************************************/
/*                       LOCAL FUNCTION DEFINITIONS                          */
/*****************************************************************************/

/*
 ** Main Function.
 */
int main(void)
{
    testSPIEdma();
    while (1)
    {

    }
}

static void testSPIEdma()
{
    /* Enable the clocks for McSPI1 module.*/
    McSPI1ModuleClkConfig();
    /* Perform Pin-Muxing for SPI1 Instance.*/
    McSPI1PinMuxSetup();
    /* Initialize the EDMA3 instance.*/
    EDMA3Initialize();
    /* Request EDMA3CC for Tx and Rx channels for SPI1. */
    RequestEDMA3Channels();
    /* Set up the McSPI instance.*/
    McSPISetUp();
    cb_Fxn[MCSPI_RX_EVENT] = &CallBack;
    /* Configure the write enable parameters for Edma receive.*/
    McSpiRxEdmaParamSet(MCSPI_RX_EVENT, MCSPI_RX_EVENT, rxBuffer, DATALENGTH, TRUE);
    McSPITransfer(DATALENGTH);
}

/*
 ** This function configures the power supply for EDMA3 Channel Controller 0
 ** and Transfer Controller 0, registers the EDMA interrupts in AINTC.
 */
static void EDMA3Initialize(void)
{
    /* Enable module clock for EDMA */
    EDMAModuleClkConfig();

    /* Initialization of EDMA3 */
    EDMA3Init(SOC_EDMA30CC_0_REGS, EVT_QUEQUE_NUM);

    /* Configuring the AINTC to receive EDMA3 Interrupts */
    EDMA3AINTCConfigure();
}

/*
 ** This function will Assert the Chip select line before transmission, will
 ** enable the Edma events for Tx/Rx of McSPI peripheral, will De-assert the
 ** Chip select once communication is complete.
 */
static void McSPITransfer(unsigned short length)
{
    /* Set the word count field with the data length to be transferred.*/
    McSPIWordCountSet(SOC_SPI_1_REGS, length);

    /* Enable the Tx/Rx DMA events for McSPI. */
    McSPIDMAEnable(SOC_SPI_1_REGS, (MCSPI_DMA_RX_EVENT),
    MCSPI_CH_NUM);

    /* Enable the McSPI channel for communication.*/
    McSPIChannelEnable(SOC_SPI_1_REGS, MCSPI_CH_NUM);

    /* Wait for control to return from ISR.*/
    while ((0 == flagTx) || (flagRx == 0))
        ;

    flagTx = 0;
    flagRx = 0;

    /* Disable the McSPI channel for communication.*/
    McSPIChannelDisable(SOC_SPI_1_REGS, MCSPI_CH_NUM);
}

/*
 ** EDMA3 completion Interrupt Service Routine(ISR).
 */
static void Edma3ComplHandlerIsr(void)
{
    unsigned int pendingIrqs;
    unsigned int isIPR = 0;
    unsigned int indexl;
    unsigned int Cnt = 0;

    indexl = 1;

    isIPR = EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS);

    if (isIPR)
    {
        while ((Cnt < EDMA3CC_COMPL_HANDLER_RETRY_COUNT) && (indexl != 0))
        {
            indexl = 0;

            pendingIrqs = EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS);

            while (pendingIrqs)
            {
                if ((pendingIrqs & 1) == TRUE)
                {
                    /**
                     * If the user has not given any callback function
                     * while requesting the TCC, its TCC specific bit
                     * in the IPR register will NOT be cleared.
                     */
                    /* Here write to ICR to clear the corresponding IPR bits. */
                    EDMA3ClrIntr(SOC_EDMA30CC_0_REGS, indexl);

                    (*cb_Fxn[indexl])(indexl, EDMA3_XFER_COMPLETE);
                }

                ++indexl;

                pendingIrqs >>= 1;
            }
            Cnt++;
        }
    }

}

/* EDMA3 Error Handler */
static void Edma3ErrorHandlerIsr(void)
{
    /* clear the pending error interrupt */
    EDMA3ClrMissEvt(SOC_EDMA30CC_0_REGS, MCSPI_TX_EVENT);

    /* Disable McSPI Transmit event */
    McSPIDMADisable(SOC_SPI_1_REGS, MCSPI_DMA_TX_EVENT, MCSPI_CH_NUM);

    /* Disable Edma Transfer */
    EDMA3DisableTransfer(SOC_EDMA30CC_0_REGS, MCSPI_TX_EVENT,
    EDMA3_TRIG_MODE_EVENT);

    flagTx = 1;

    /* clear the pending error interrupt */
    EDMA3ClrMissEvt(SOC_EDMA30CC_0_REGS, MCSPI_RX_EVENT);

    /* Disable McSPI Receive event */
    McSPIDMADisable(SOC_SPI_1_REGS, MCSPI_DMA_RX_EVENT, MCSPI_CH_NUM);

    /* Disable Edma Transfer */
    EDMA3DisableTransfer(SOC_EDMA30CC_0_REGS, MCSPI_RX_EVENT,
    EDMA3_TRIG_MODE_EVENT);

    flagRx = 1;

}

/*
 ** Call back function. Here we disable the Tx/Rx DMA events of McSPI
 ** peripheral.
 */
static void CallBack(unsigned int tccNum, unsigned int status)
{

    if (tccNum == MCSPI_RX_EVENT)
    {
        flagRx = 1;

        /* Disable McSPI Receive event */
        McSPIDMADisable(SOC_SPI_1_REGS, MCSPI_DMA_RX_EVENT, MCSPI_CH_NUM);
    }
}

/*
 ** This function is used to set the PaRAM entries of EDMA3 for the Receive
 ** event of channel 0 of McSPI0 instance. The corresponding EDMA3 channel
 ** is also enabled for reception.
 */
static void McSpiRxEdmaParamSet(unsigned int tccNum, unsigned int chNum,
                                volatile unsigned char *buffer,
                                unsigned short buffLength,
                                unsigned int destBidxFlag)
{
    EDMA3CCPaRAMEntry paramSet;

    unsigned char *p = (unsigned char *) &paramSet;
    unsigned int index = 0;

    /* Clean-up the contents of structure variable. */
    for (index = 0; index < sizeof(paramSet); index++)
    {
        p[index] = 0;
    }

    /* Fill the PaRAM Set with Receive specific information.*/

    /* srcAddr holds address of SPI Rx FIFO.*/
    paramSet.srcAddr = (unsigned int) (MCSPI_RX0_REG);

    /* destAddr is address of memory location named buffer.*/
    paramSet.destAddr = (unsigned int) buffer;

    /* aCnt holds the number of bytes in an array.*/
    paramSet.aCnt = 2;

    /* bCnt holds the number of such arrays to be transferred.*/
    paramSet.bCnt = FIFORX >> 1;

    /* cCnt holds the number of frames of aCnt*bBcnt bytes to be transferred.*/
    paramSet.cCnt = DATALENGTH / paramSet.bCnt;

    /* The srcBidx should not be incremented since it is a h/w register.*/
    paramSet.srcBIdx = 0;

    if (TRUE == destBidxFlag)
    {
        /* The destBidx should be incremented for every byte.*/
        paramSet.destBIdx = paramSet.aCnt;
    }
    else
    {
        /* The destBidx should not be incremented.*/
        paramSet.destBIdx = 0;
    }

    /* A sync Transfer Mode. */
    /* srCIdx and destCIdx set to zero since ASYNC Mode is used.*/
    paramSet.srcCIdx = 0;
    /*TODO: rxtrig or 0*/
    paramSet.destCIdx = FIFORX;

    /* Linking transfers in EDMA3 are not used.*/
    paramSet.linkAddr = 0xFFFF;

    paramSet.bCntReload = paramSet.bCnt;

    paramSet.opt &= 0xFFFFFFFCU;
    paramSet.opt &= 0xFFFFF8FFU;
    paramSet.opt |= 0x4U;
    paramSet.opt &= (~EDMA3CC_OPT_TCC);
    /* Set TCC field in OPT with the tccNum.*/
    paramSet.opt |= ((tccNum << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);


    /* EDMA3 Interrupt is enabled and Intermediate Interrupt Disabled.*/
    paramSet.opt |= (1 << EDMA3CC_OPT_TCINTEN_SHIFT);

    /* Now write the PaRam Set to EDMA3.*/
    EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, chNum, &paramSet);

    /* EDMA3 Transfer is Enabled.*/
    EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, chNum, EDMA3_TRIG_MODE_EVENT);
}

/*
 ** This function allocates EDMA3 channels to McSPI0 for trasmisssion and
 ** reception purposes.
 */
static void RequestEDMA3Channels(void)
{
    /* Request DMA Channel and TCC for SPI Transmit*/
//    EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA, \
//                        MCSPI_TX_EVENT, MCSPI_TX_EVENT, EVT_QUEQUE_NUM);
    /* Request DMA Channel and TCC for SPI Receive*/
    EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
    MCSPI_RX_EVENT,
                        MCSPI_RX_EVENT, EVT_QUEQUE_NUM);
}

/*
 ** This function will call the necessary McSPI APIs which will configure the
 ** McSPI controller.
 */
static void McSPISetUp(void)
{
    /* Reset the McSPI instance.*/
    McSPIReset(SOC_SPI_1_REGS);

    MCSPISysConfigSetup(SOC_SPI_1_REGS, MCSPI_CLOCKS_OCP_ON_FUNC_ON,
    MCSPI_SIDLEMODE_NO,
                        MCSPI_WAKEUP_DISABLE,
                        MCSPI_AUTOIDLE_OFF);
    /* Enable chip select pin.*/
    McSPICSEnable(SOC_SPI_1_REGS);

    /* Enable master mode of operation.*/
    /*Slave mode enable*/
    //McSPIMasterModeEnable(SOC_SPI_1_REGS);
    McSPISlaveModeEnable(SOC_SPI_1_REGS);
    /* Perform the necessary configuration for master mode.*/

    MCSPIPinDirSet(SOC_SPI_1_REGS, MCSPI_RX_ONLY_MODE,
                   MCSPI_DATA_LINE_COMM_MODE_7, 0);

    MCSPIMultiChModeEnable(SOC_SPI_1_REGS);
    /* Configure the McSPI output frequency. */
    McSPIClkConfig(SOC_SPI_1_REGS, MCSPI_IN_CLK, MCSPI_OUT_FREQ,
    MCSPI_CH_NUM,
                   MCSPI_CLK_MODE_0);

    /* Configure the word length.*/
    McSPIWordLengthSet(SOC_SPI_1_REGS, MCSPI_WORD_LENGTH(16), MCSPI_CH_NUM);

    /* Set polarity of SPIEN to low.*/
    McSPICSPolarityConfig(SOC_SPI_1_REGS, MCSPI_CS_POL_LOW, MCSPI_CH_NUM);

    /* Enable the Tx FIFO of McSPI.*/
    McSPITxFIFOConfig(SOC_SPI_1_REGS, MCSPI_TX_FIFO_DISABLE, MCSPI_CH_NUM);

    /* Enable the Rx FIFO of McSPI.*/
    McSPIRxFIFOConfig(SOC_SPI_1_REGS, MCSPI_RX_FIFO_ENABLE, MCSPI_CH_NUM);

    McSPIFIFOTrigLvlSet(SOC_SPI_1_REGS, FIFORX, 0, MCSPI_RX_ONLY_MODE);
}

/*
 ** This function configures the AINTC to receive EDMA3 interrupts.
 */
static void EDMA3AINTCConfigure(void)
{
    /* Enable IRQ in CPSR.*/
    IntMasterIRQEnable();
    /* Initializing the ARM Interrupt Controller. */
    IntAINTCInit();

    /* Registering EDMA3 Channel Controller 0 transfer completion interrupt.  */
    IntRegister(SYS_INT_EDMACOMPINT, Edma3ComplHandlerIsr);

    /* Setting the priority for EDMA3CC0 completion interrupt in AINTC. */
    IntPrioritySet(SYS_INT_EDMACOMPINT, 0, AINTC_HOSTINT_ROUTE_IRQ);

    /* Enabling the EDMA3CC0 completion interrupt in AINTC. */
    IntSystemEnable(SYS_INT_EDMACOMPINT);

    /* Registering EDMA3 Channel Controller 0 Error Interrupt. */
    IntRegister(SYS_INT_EDMAERRINT, Edma3ErrorHandlerIsr);

    /* Setting the priority for EDMA3CC0 Error interrupt in AINTC. */
    IntPrioritySet(SYS_INT_EDMAERRINT, 0, AINTC_HOSTINT_ROUTE_IRQ);

    /* Enabling the EDMA3CC0 Error interrupt in AINTC. */
    IntSystemEnable(SYS_INT_EDMAERRINT);
}

/*
 ** This configures the PaRAM set for the Dummy Transfer.
 */
static void TxDummyPaRAMConfEnable(void)
{
    EDMA3CCPaRAMEntry dummyPaRAMSet;

    EDMA3GetPaRAM(SOC_EDMA30CC_0_REGS, DUMMY_CH_NUM, &dummyPaRAMSet);

    dummyPaRAMSet.aCnt = 1;
    dummyPaRAMSet.bCnt = 0;
    dummyPaRAMSet.cCnt = 0;
    dummyPaRAMSet.srcAddr = 0;
    dummyPaRAMSet.destAddr = 0;
    dummyPaRAMSet.srcBIdx = 0;
    dummyPaRAMSet.destBIdx = 0;
    dummyPaRAMSet.srcCIdx = 0;
    dummyPaRAMSet.destCIdx = 0;
    dummyPaRAMSet.linkAddr = 0xFFFFu;
    dummyPaRAMSet.bCntReload = 0;
    dummyPaRAMSet.opt = 0;

    EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, DUMMY_CH_NUM, &dummyPaRAMSet);
}

0 David Schmittwilken over 8 years ago in reply to David Schmittwilken

Intellectual 300 points

DMA issue fixed. The MOSI cable was unplugged... . Everything works as expected.

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PROCESSOR-SDK-AM335X: SPI receive not working