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AM3352: DDR3 PHY register configuration

Brandon08
Mastermind 24190 points
Part Number: AM3352

Team, I'm working through the following DDR PHY register configuration wiki http://processors.wiki.ti.com/index.php/AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling and am modifying the gel file contained on that page for the starter kit EVM. The process is working well using the Samsung device K4B2G1646F-BYMA and I have two questions:

  1. Does the gel file set the DDR3 clock frequency or is this a function of hardware straps and xtal osc freq?  I need to make sure I’m running the DDR interface at 400MHz (short of probing with a fast and cumbersome scope) rather than 303MHz as stated in the gel file.

  2. The AM335x DDR Register Calc spreadsheet requires an  ODT low on parameter (REG_T_ODT).  This is not listed on Samsung data sheet.  Parameter in highlighted in RED below.  How can I get this parameter?  Can this be calculated indirectly from other listed parameters on the Samsung data sheet?

Your guidance is welcome. Thank you!

  • 0
    TI__Guru**** 393215 points
    The factory team have been notified. They will respond here.
  • 0
    TI__Genius 9655 points

    DEEP SEARCH said:
    1. Does the gel file set the DDR3 clock frequency or is this a function of hardware straps and xtal osc freq?  I need to make sure I’m running the DDR interface at 400MHz (short of probing with a fast and cumbersome scope) rather than 303MHz as stated in the gel file.

    I'm not sure which version of the GEL file you are using, but when you connect to the target, the routine GetInputClockFrequency() should be able to detect the boot pins to figure out the right crystal frequency and then set the frequency. Do note that you would have to modify the GEL file if the DDR PLL is set to 303 MHz instead of 400 MHz depending on which version of the GEL file you are using. You can simply search for  DDR_PLL_Config in the GEL file and set the frequency to the right value.

    DEEP SEARCH said:

    2. The AM335x DDR Register Calc spreadsheet requires an  ODT low on parameter (REG_T_ODT).  This is not listed on Samsung data sheet.  Parameter in highlighted in RED below.  How can I get this parameter?  Can this be calculated indirectly from other listed parameters on the Samsung data sheet?

    ODTLon is a JEDEC parameter and should be part of the DRAM data sheet. I'm unsure why the specific DRAM part does not list this. You may want to check with the DRAM manufacturer regarding the same. Per JEDEC spec, this should be [CWL + AL - 2] tck. For instance, if CWL = 5tCK, AL = 0; ODTL should be set as 3tCK
    Let me know if you have any additional questions.
    Regards, Siva

  • 0 in reply to sivak
    Intellectual 260 points

    AM3358_StarterKit.gelInput clock frequency is 24Mhz.  I'm using the SDK EVM file (attached).  How to set DDR PLL so DRAM clock frequency is 400MHz?  Currently it is at 303MHz.    This had been confirmed with a scope measurement.

    Rgds,

    John

  • 0 in reply to John Chiu
    TI__Genius 9655 points
    Change:

    DDR_PLL_Config( CLKIN, 23, 303, 1);

    to:

    //Configuration for 400MHz
    DDR_PLL_Config( CLKIN, 23, 400, 1);

    Regards, Siva