DM648 Video Port

I see  so many members of "VPORTCAP_ParamsRaw" structure are not initialized - like lineSz, numLines, thrld etc.

One of the main parameter of this structure "cmode" should be set to VPORT_MODE_RAW_16BIT for 16-bit raw capture operation.

Hi

Thanks for your reply. I have missed the initialisation part in my previous post. i am initialising the vCapParamsChanRaw's member with valid vales. 

#define NUM_PIXELS 1024 // Number of Horizontal Pixels

#define NUM_LINES 768 // Number of Lines

#define FRAME_BYTES_SIZE NUM_PIXELS*NUM_LINES*2 // Frame size in bytes

VPORTCAP_ParamsRaw vCapParamsChanRaw=

{

VPORT_MODE_RAW_16BIT, // cmode - capture mode

VPORTCAP_BPK_10BIT_ZERO_EXTENDED, // bpk10Bit

TRUE, // startupSyncEnable

1000, // blankperiod

NUM_PIXELS>>1, // number of pixels per line

NUM_LINES, // number of lines per frame

(NUM_PIXELS>>4), // thrld

// - FIFO threshold value indicates number of double words to generate DMA events.

//   This value is normally equivalent to line size divided by 8.

0, // numFrmBufs

128, // alignment - frame buffer alignment

NULL, // segId

// - memory segment ID, used by driver to allocate video frame buffer.

NULL // hEdma - EDMA3 driver handle

};

is it possible for you to send me a very simple Vport example code / project without using XDC. 

Thanks

Update:

Now i have a handle for the Videoport 2 device. i am configuring it to be in 16Bit Raw capture mode. but if i look at the VP2 Registers from CCS, VCA_CTL registers are not updated. they are with default values. if i goto the next step, to strat capture it fails. 

while getting the handle from FVID_create i get the status as "-5" i am not sure what i am missing. please can anyone post me a working vport example. 

Thanks

Logadeepan

Sample application to illustrate 16-bit RAW capture is available in the PSP driver package @ "pspdrivers_1_10_XX\packages\ti\sdo\pspdrivers\system\dm648\bios\evmDM648\video\sample\build\raw_capture_loopback".

Let me know if this helps.

Hi

Thanks for the reply. I have tried that example already. i have also used that example to write my code. the problem is same. after FVID_create the video port registers(Port CTL and channel CTL)  are not set to correct values.  they are with default values. 

i am sure VP2 is enabled from the PSC so i can see some values on the VP2 registers, whereas for VP1 , VP3 etc the values are 0.

i have also tried a lowlevel approch to set the VP registers. they are working fine. i can initialise the registers, even i can see the data in the PDIN register.

If you need further info please let me know.

Thanks in advance

Logadeepan

Have you tried using the sample application?

Are you using any custom board? What is that are you trying to achieve? Give me an overview of the use case.

If possible can you step in to the driver function and see exactly where this is failing?

Hi

We are using a custom board. we have a FPGA reading a image sensor and transfering 16 bit RAW video data to Video port 2 of DM648.  resolution of the image is 1280 x 1024. 

Looking at the driver level it seems it fails during the EDMA3_DRV_getPaRAMPhyAddr in the channel create function of vportcap.c. looking further in edma3.c EDMA3_DRV_getPaRAMPhyAddr fails because the "lCh" parameter (1005) is greater than the EDMA3_DRV_LOG_CH_MAX_VAL. 

also EDMA3_DRV_requestChannel in the vportcap.c fails with error.

Thanks

Logadeepan

Have you EDMA driver initialization as done in the sample application in tskInit() function?

Will you be able to share the test application?

I am especially looking for the VPORT create parameters.

I have found the main problem. its because of the version compatibility issue with Video port driver and Edma driver. i tried downloading latest versions of both. now the video port registers are setup by the driver. i can also see the video capture bit enabled when i send start capture command. 

now i have a different problem, once i start capture and then try the FVID_dequeue it hangs for ever. it seems its waiting for the frame to be received. but the VC_XPOS and VC_YPOS (data counter) seems to be incrementing. also i can see the PDIN register changing. i have also tried looking at the YSRCA Fifo register, values are always 0.

I have also attached the code i am using. if you could comment, that would very helpful

Thanks again

I went through the code and things seems to be fine.

I need the following information to debug this further.

1. How are the control signals connected to VPORT? Basically I am looking for the EVM layout with respect to VPORT data and control signals.

2. Could you explain about the timings of these controls signals?

Hope you have connected CAPEN signal to the VPORT instead of VSYNC & HSYNC and following the timings and connection as explained for RAW capture in VPORT datasheet.

Update: 

On the code i posted before I did the following changes

1) Start capture

2) wait for a 9000000 cycles,

3) stop capturing

4) Read the EDMA channel 6 Destination address register

5) copy the data from the EDMA Destination address.

by doing the above i get a full frame image without any loss / syncronisation problems.

i know this is not the solution atleast this prooves valid image data is transfered from the FPGA and Video Port driver also kicks the EDMA transfer.

I have also checked the signals. CAPEN is used instead of VSYNC / HSYNC. we are using siilar layout as EVM. 

Thanks 

Logadeepan

Hi

Still dint fix the problem. By any chance is it to do anything with the known issue with EDMA3 driver. Just looked at the EDMA driver release notes. 

"EDMA3 hardware doesn’t works properly in FIFO mode with all the controllers."

Thanks

Logadeepan

Finally i end up writing my own low level Video port driver and using the EDMA PSP driver. now it works fine in full frame rate. I am not still sure whats wrong with the TI's Vport PSP Driver.

Logadeepan

We are running into the same issue.  We found a work-around to get past the first FVID_dequeue by ungating the video clock (running it continuously even when capen is not enabled) to start then gating the clock a number of frames.  But then we are having problems correctly syncing.  The driver does not seem to flush out or correctly restart edma on a new capen.  Are you willing to share your re-written driver code?