RTOS/TMS320C6678: Why is evmc6678.gel and ibl.ddrConfig.uEmif.emif4p0 in iblConfig.gel different for the same DDR3 controller?

TI RTOS SDK: ti processor sdk rtos c667x evm 04.02.00.09

iblConfig.gel: <ti_install> / pdk_c667x_2_0_8 / packages / ti / boot / ibl / src / make / bin

We know the location in the evmc6678l.gel file.

The following is the part of configuring ddr3 controller in evmc678l.gel.

The next step is to configure emif4 in iblConfig.gel.

I want to know exactly what I am mistaken.

In summary

===========================================================

=                               =   evmc6678l.gel                       = iblConfig.gel

===========================================================

=   SDTIM1            = 0x1113783C                              = 0x0AAAE51B

=   SDTIM2            = 0x30717FE3                              = 0x2A2F7FDA

=   SDTIM3            = 0x559F86AF                              = 0x057F82B8

=   DDRPHYC       = 0x0010010F                              = 0x0010010d

=   SDCFG             = 0x63222A32                              = 0x63C452B2

=   SDRFC             = 0x00005162, 0x00001450    = 0x000030D4

============================================================

I think the parameter in evmc6678l.gel seems to be correct.

If so, should iblConfig.gel be modified?

Is that what I think?

==============================================================

= evmc6678l.gel

==============================================================

    / ***************** 3.4 Basic Controller and DRAM Configuration ************ /

    DDR_SDRFC = 0x00005162; // enable configuration

    / * DDR_SDTIM1 = 0x1113783C; * /

    TEMP = 0;

    TEMP | = 0x8 << 25; // T_RP bit field 28:25

    TEMP | = 0x8 << 21; // T_RCD bit field 24:21

    TEMP | = 0x9 << 17; // T_WR bit field 20:17

    TEMP | = 0x17 << 12; // T_RAS bit field 16:12

    TEMP | = 0x20 << 6; // T_RC bit field 11: 6

    TEMP | = 0x7 << 3; // T_RRD bit field 5: 3

    TEMP | = 0x4; // T_WTR bit field 2: 0

    DDR_SDTIM1 = TEMP;

    / * DDR_SDTIM2 = 0x30717FE3; * /

    TEMP = 0;

    TEMP | = 0x3 << 28; // T_XP bit field 30:28

    TEMP | = 0x71 << 16; // T_XSNR bit field 24:16

    TEMP | = 0x1ff << 6; // T_XSRD bit field 15: 6

    TEMP | = 0x4 << 3; // T_RTP bit field 5: 3

    TEMP | = 0x3; // T_CKE bit field 2: 0

    DDR_SDTIM2 = TEMP;

    / * DDR_SDTIM3 = 0x559F86AF; * /

    TEMP = 0;

    TEMP | = 0x5 << 28; // T_PDLL_UL bit field 31:28 (fixed value)

    TEMP | = 0x5 << 24; // T_CSTA bit field 27:24 (fixed value)

    TEMP | = 0x4 << 21; // T_CKESR bit field 23:21

    TEMP | = 0x3f << 15; // T_ZQCS bit field 20:15

    TEMP | = 0x6a << 4; // T_RFC bit field 12: 4

    TEMP | = 0xf; // T_RAS_MAX bit field 3: 0 (fixed value)

    DDR_SDTIM3 = TEMP;

    DDR_DDRPHYC = 0x0010010F;

    DDR_ZQCFG = 0x70073214;

    DDR_PMCTL = 0x0;

    DDR_SDRFC = 0x00005162; // enable configuration

    / * DDR_SDCFG = 0x63062A32; * /

    / * New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ / 7 // 0x63222A32; // last config write DRAM init occurs * /

    TEMP = 0;

    TEMP | = 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value)

    TEMP | = 0x0 << 27; // IBANK_POS bit field 28:27

    TEMP | = 0x3 << 24; // DDR_TERM bit field 26:24

    TEMP | = 0x0 << 21; // DYN_ODT bit field 22:21

    TEMP | = 0x1 << 18; // SDRAM_DRIVE bit field 19:18

    TEMP | = 0x2 << 16; // CWL bit field 17:16

    TEMP | = 0x0 << 14; // NM bit field 15:14

    TEMP | = 0xA << 10; // CL bit field 13:10

    TEMP | = 0x4 << 7; // ROWSIZE bit field 9: 7

    TEMP | = 0x3 << 4; // IBANK bit field 6: 4

    TEMP | = 0x0 << 3; // EBANK bit field 3: 3

    TEMP | = 0x2; // PAGESIZE bit field 2: 0

    DDR_SDCFG = TEMP;

    // Wait 600us for HW init to complete

    Delay_milli_seconds (1);

    DDR_SDRFC = 0x00001450; // Refresh rate = (7.8 * 666 MHz)

=============================================================

==============================================================

= iblConfig.gel

==============================================================

ibl.ddrConfig.configDdr = 1;

ibl.ddrConfig.uEmif.emif4p0.registerMask = ibl_EMIF4_ENABLE_sdRamConfig | ibl_EMIF4_ENABLE_sdRamRefreshCtl | ibl_EMIF4_ENABLE_sdRamTiming1 | ibl_EMIF4_ENABLE_sdRamTiming2 | ibl_EMIF4_ENABLE_sdRamTiming3 | ibl_EMIF4_ENABLE_ddrPhyCtl1;

ibl.ddrConfig.uEmif.emif4p0.sdRamConfig = 0x63C452B2;

ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2 = 0;

ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl = 0x000030D4;

ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1 = 0x0AAAE51B;

ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2 = 0x2A2F7FDA;

ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3 = 0x057F82B8;

ibl.ddrConfig.uEmif.emif4p0.lpDdrNvmTiming = 0;

ibl.ddrConfig.uEmif.emif4p0.powerManageCtl = 0;

ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic = 0;

ibl.ddrConfig.uEmif.emif4p0.performCountCfg = 0;

ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel = 0;

ibl.ddrConfig.uEmif.emif4p0.readIdleCtl = 0;

ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet = 0;

ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg = 0;

ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg = 0;

ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1 = 0x0010010d;

ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2 = 0;

ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap = 0;

ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map = 0;

ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map = 0;

ibl.ddrConfig.uEmif.emif4p0.eccCtl = 0;

ibl.ddrConfig.uEmif.emif4p0.eccRange1 = 0;

ibl.ddrConfig.uEmif.emif4p0.eccRange2 = 0;

ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh = 0;

==============================================================

Thanks for the reply.

Sorry.

I do not speak English well.
So you did not understand what I was saying.

I'm curious.
Is the emfi4 (ddr3) parameter in iblConfig.gel correct?

Why is the ddr3 parameter different from emvc6678l.gel?

Below is the ddr3 parameter value extracted from each gel.

Sorry for the misunderstanding. I am looping the RTOS team to elaborate.

Best Regards,
Yordan