Part Number: AM3358
The hardware I am working with requires a 500ns "disable" time between transfers (one start bit + 20 bit word), and I need to do them in batches of up to 8 transfers. I currently intend to use the FIFO, load all 8 words after getting a timer interrupt, and get one single interrupt when all 8 are done. I'd rather not do them one by one if possible to minimize interrupts.
However there doesn't seem to be an option for this. The "chip select time control" does not control the time of the chip select, it controls the time around the chip select. It also doesn't do the "first or last edge", it does the first and last edge, with no option that I can see to pick one only.
As a side note, the reference manual implies that automatic CS generation is controlled by "FORCE", but it seems that "FORCE" is just to assert CS when already in manual mode, and automatic CS mode is controlled by putting the SPI in multi-channel mode (even if only one channel is used), which is weird to say the least.
My current plan is to set the pre-and-post-CS-delay to the maximum amount, then use external circuitry (eg. a pulse stretcher) to make the high-to-low transition slower. I might also try DMA as that may inadvertently increase the time, as in this thread:
Is there an easier way to do this that I'm missing?
Thanks.
