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AM5728: VIP used as raw data interface

Other Parts Discussed in Thread: AM5728

We are designing a board using the AM5728's VIP port to input data from FPGA. Using the am572x IDK board, I am writing a test application to collect data from IDK board J9 camera port. However, the data is not from the camera but from other board that sending raw 8 bit data along with PCLK, VSYNC, and ACTIVID signals.

The test app is modified from TI's loopback example and I am following the instruction/suggestions from the link below. The issue is that I could not get any data -- The Driver callback function LpbkApp_captCbFxn is not called to notify the new frame arrival.

https://e2e.ti.com/support/arm/sitara_arm/f/791/t/573975?tisearch=e2e-sitesearch&keymatch=am5728%20vip%20raw

These are my basic settings and no other internal processing blocks of VIP like scaling, format conversion, and color conversion etc should be used

videoIfMode  = FVID2_VIFM_SCH_DS_AVID_VSYNC;  videoIfWidth = FVID2_VIFW_8BIT

vipPrms->inFmt.width = 1000;   vipPrms->inFmt.height = 2; // we only have two lines per frame

vipPrms->inFmt.dataFormat      = FVID2_DF_RAW08;

I attached my test project file. Please advise what configuration that I should use to get the raw data input.

Thanks.

vip_8bit_raw.zip

  • Hello,

    What is the software release that you are using here?
    Please check this guide:
    processors.wiki.ti.com/.../Linux_Core_VIP_User's_Guide

    BR
    Margarita
  • We are not using Linux for this project. We use TI-RTOS pdk_am57xx_1_0_9 and went through all the examples in link
    processors.wiki.ti.com/.../Processor_SDK_RTOS_VPS_DRIVERS

    My project files are attached in my first post, please advise what configuration that I should use to get the raw data input.

    Thanks
  • Hi,

    Was the original loopback or vip capture test working with IDK AM572x EVM + OV 2659 camera, then you changed the input data from FPGA?

    Regards, Eric
  • Yes, the loopback works fine with IDK am572x evm + OV2659 camera. Then I removed the camera and the input data now from the FPGA. In my first post, the attached files has the code changes I made to acquire the raw data input.
    Thanks,
  • Hi,

    Under the main.c, for the global setup:
    FVID2_STD_720P_60,
    /* dispStandard */
    {
    FVID2_STD_CUSTOM,
    },

    FVID2_VIFM_SCH_DS_HSYNC_VSYNC, /* captVideoIfMode */
    FVID2_VIFW_8BIT, /* captVideoIfWidth */
    FVID2_SF_PROGRESSIVE, /* captScanFormat */
    FVID2_DF_YUV422P, /* captInDataFmt */
    FVID2_DF_YUV422I_UYVY, /* captOutDataFmt */

    LPBK_APP_SC_DISABLE_ALL, /* captScEnable */
    1280U, /* captInWidth */
    720U, /* captInHeight */

    Can you set captVideoIfMode = FVID2_VIFM_SCH_DS_AVID_VSYNC;
    captInWidth = 1000 and captInHeight = 2. I knew in your initialization code you set them correctly. But please set them here as well as they may be used at other places, let us know if you have the capture callback working.

    Regards, Eric
  • I made the changes and the capture callback is not working. Please the attached zip for current project files.

    Thank you.

    vps_8bit_raw_v2.zip

  • Hi,

    Sorry for the late! We looked the code, it is a cutdown of VPS loopback example without the display part, it seems OK. In the configuration code, videoIfMode = FVID2_VIFM_SCH_DS_AVID_VSYNC

    What is the capture interface? I am not sure if this is correct (Wondering if you need to keep it as: FVID2_VIFM_SCH_DS_AVID_VBLK or something else) as you are not getting interrupts.

    You can go through section under AM572x TRM “9.4.5.19 Discrete Sync Signals” to get the correct sync signal type, then check the enumeration Fvid2_VideoIfMode in fvid2_dataTypes.h.

    Also, as you change many codes in main.c and test.c, I wonder if you can look at the pdk_am57xx_1_0_9\packages\ti\drv\vps\examples\vip\captureVip\src\capturevip_main.c as the reference as you don't need the display part.

    Regards, Eric