AM3505 GPMC_FCLK

I think initially yes, but the ROM ultimately sets up the GPMC for 48MHz operation

Regards,

James

James,

We agree that the ROM configures the external GPMC_CLK to run at 48MHz out of reset or on a power on cycle.  We want to validate that the ROM configures the GPMC_FCLK for 96MHz operation at this time.  The TRM references the L3.ICLK default clock to be 96MHz (see page 2700).  Would you also confirm that GPMC_FCLK is sourced by the L3.ICLK clock?

Thanks,

Ken

Yes, GPMC_FCLK comes from L3_ICLK.

Regards,

James

Ken Turocy said:

Immediately after a power on cycle or hardware reset, is the GPMC_FCLK running at the same frequency as the L3, ICLK (96MHz)?

The GPMC_FCLK is sourced by the CORE_L3_ICLK which is sourced by the L3_ICLK, however it does not seem that it would be 96MHz immediately, though that is the default clocking configuration put in place by the ROM code. There would be some time (which may not be deterministic depending on PLL locking times) before the ROM code configures the PLL and the PLL stabilizes after power on reset to get to 96MHz.

I am not sure what the GPMC_FCLK frequency would be before the ROM code gets involved, I traced it down to L3_ICLK = (((SYS_CLK * CORE_DPLL_MULT) / (CORE_DPLL_DIV + 1)) / CORE_DPLL_CLKOUT_DIV) / CLKSEL_L3 which filling in the defaults gives L3_ICLK = (((13MHz * 0) / (0+1) / 1 / 1. This leads me to suspect it will start as 13MHz if it is initially active at all since the default value for CORE_DPLL_MULT is 0, which is ambiguous for a PLL (I am not sure if it means it is disabled or defaulting to a pass through). In any case this is something that is dealt with by the ROM code automatically at boot, so the timing of the GPMC_FCLK coming up is not well defined.

If you could elaborate more on why this is of interest, we may be able to help out with the underlying problem?

EDIT: It looks like this thread was quite active while I was trying to trace down the clock in the TRM, I apologize if this post is already obsolete...