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AM5728: Purpose of MAILBOX_IRQ_EOI register

Daniel Castagnola Weckesser
Intellectual 410 points
Part Number: AM5728

Hi,

What's the purpose of the register MAILBOX_IRQ_EOI (page #5517 of TRM)  and its related PDK function MailboxWriteEOI ?

All the TRM says about is "This register is used for the software EOI clearance of the pulse", so does it have the same function than register MAILBOX_IRQSTATUS_CLR_u pointed by TRM to clear the interrupt request ? 

Thanks,

Daniel

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 95265 points
    Hi,

    From the TRM, 19.3.4 Mailbox Interrupt Requests

    An event can generate an interrupt request when a logical 1 is written to the corresponding unmask bit in
    the MAILBOX_IRQENABLE_SET_u register. Events are reported in the appropriate
    MAILBOX_IRQSTATUS_CLR_u and MAILBOX_IRQSTATUS_RAW_u registers.
    An event stops generating interrupt requests when a logical 1 is written to the corresponding mask bit in
    the MAILBOX_IRQENABLE_CLR_u register. Events are only reported in the appropriate
    MAILBOX_IRQSTATUS_RAW_u register.
    In case of the MAILBOX_IRQSTATUS_RAW_u register, the event is reported in the corresponding bit
    even if the interrupt request generation is disabled for this event.

    Reading the MAILBOX_IRQSTATUS_CLR_u register determines the status of the new message and the
    queue-not-full interrupts for a particular user. Writing 1 to the corresponding bit in the
    MAILBOX_IRQSTATUS_CLR_u register acknowledges, and subsequently clears, an interrupt.

    The CSL code has a function API MailboxWriteEOI, there is no application example what should be done inside an mailbox ISR. From our other peripherals ISR examples, both Status and EOI registers need to be written. So this should be the same for mailbox ISR, that is, MailboxClrNewMsgStatus() and MailboxWriteEOI() needs to be called in the ISR to clear the interrupt.

    Regards, Eric