Linux/AM4376: 16MB super section and 64KB large page support

Hi Lawrence,

Could you specify which Linux release you are using?

BR
Tsvetolin Shulev

linux-4.9.28-rt

For the Ioremap of 16MB region, just need to apply the following patch.

Index: arch/arm/mm/ioremap.c
===================================================================
--- arch/arm/mm/ioremap.c (revision 625)
+++ arch/arm/mm/ioremap.c (working copy)
@@ -316,6 +316,9 @@
!((paddr | size | addr) & ~SUPERSECTION_MASK)) {
area->flags |= VM_ARM_SECTION_MAPPING;
err = remap_area_supersections(addr, pfn, size, type);
+ } else if ((cpu_architecture() == CPU_ARCH_ARMv7) && !((paddr | size | addr) & ~SUPERSECTION_MASK)) {
+ area->flags |= VM_ARM_SECTION_MAPPING;
+ err = remap_area_supersections(addr, pfn, size, type);
} else if (!((paddr | size | addr) & ~PMD_MASK)) {
area->flags |= VM_ARM_SECTION_MAPPING;
err = remap_area_sections(addr, pfn, size, type);

I am looking for how to setup 2nd level page table for 64KB pte size.

As an embedded system, we have FPGA and few other devices that are connected on GPMC which is 16MB and 64KB memory mapped.

Application processes actively read/write to these FPGAs and devices.

Performance matter. The lesser TLB miss, the better for an overload embedded system.

Not, this is not what I am looking for. This memory locking API is for a system which has swap device, that is like having a partition of hard drive configured as swap space, and do not allow some thread's program and/or data swap out to disk. 

In most of the embedded system, there is no swap device configured anyway. Every thread's program, data, and stack are already loaded in and run from memory (i.e. DDR).

Besides, I am talking about configuring the ARM MMU to map a device's IO space (i.e. memory mapped) with fewer page table entries (i.e. PTEs) ,  so it will have a lesser TLB miss.

The Translation Lookaside Buffer inside ARM can only store up to  32 PTEs in micro TLB, and  2-way associated 2x32 or 2x64 PTEs in main TLB, depending on hardware implementation. 

Clearly, if my program is randomly accessing the FPGA which is ioremapped to  64K  memory window  (i.e. 16 PTEs with 4K window each), it will trigger lots of TLB misses. 

Base on what I understand, a PTE which can be found in micro TLB takes lesser than few clock cycle to do the translation. If this translation misses, ARM cpu will try to find the PTE in main TLB, it will take around 10 to 20 clock cycles. If the main TLB still misses, it will trigger a page walk to find that PTE in main memory, which usually takes 100+ clock cycles. And these 100+ clock cycles are wasted time because the entire CPU is halted to wait for the page translation.

So if a 64Kbyte window can be covered by a single 64K PTE will reduce the TLB misses and the performance of the real-time system will be improved.

Thank you for the reply. 

No,  I have not asked this question to the ARM Linux.

I consider we are just the end-user of the TI Linux, not part of the open source Linux development committee. 

My impression is that TI Linux is part of Linux development committee, and actively involving Linux technology.

Cheers,

Lawrence