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AM4372: PLL lock time

Sh.Sasaki
Guru 13625 points

Part Number: AM4372

Hi all,

I'd like to know the PLL lock time (the time when PRCM_CM_IDLEST_DPLL_MPU Register [ST_DPLL_CLK] = 1) from bypass mode.

I saw the following description of TRM.

Which time is after "Frequency Relock Time" and "Phase Relock Time" when ST_DPLL_CLK becomes "1"(DPLL is locked)?

Best regards,

Sasaki

  • 0
    TI__Guru**** 393215 points
    This is described above the table:

    "Table 6-25 describes the relock times and power consumption for the PLL bypass modes, for nominal process at 30°C. Frequency Lock Time is the maximum latency from the bypass mode to when the internal normal clk frequency is within +/-1% of the final output frequency, of Active and Locked mode. Phase Lock Time is the maximum latency from the bypass mode to when, internally, the phase difference between FBCLK and REFCLK is less than 6–12% of the REFCLK period for 96 continuous REFCLKs, of Active and Locked mode."
  • 0 in reply to Biser Gatchev-XID
    Guru 13625 points
    Which of"Frequency Lock Time" and "Phase Lock Time" sets ST_DPLL_CLK of PRCM_CM_IDLEST_DPLL_MPU Register to 1?
  • 0 in reply to Sh.Sasaki
    TI__Guru* 95831 points
    The ST_DPLL_CLK bit is a combination of both the FREQUENCY and PHASE output signals of the PLL.

    Regards,
    James