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AM5728: EMIF connections

Blake Carpenter
Expert 7245 points

Part Number: AM5728

Hi,

I have a customer with the following question:

We have a question regarding the usage of the DDR EMIF’s on the dual-core AM5728.  From what I can see in the TRM you have some flexibility in how the EMIF’s are used/configured.  For example, you can assign a specific EMIF to a processor, operate them independently or have them interleaved with both processors having access to both.

 

Our desire is to keep the DDR3 memory at 2GByte max and only use two devices.  To support 32-bit we have to use two 16-bit parts.  So the question is this:  Can we place 2GByte of memory on a single EMIF and assign each core to use that single EMIF? Can the internal bus fabric handle this along with cacheing and data coherency?  I am specifically looking to see if this has been done and what the result were.  Is this something the factory could test for us if no one has tried it?

 

Secondly, if we use data interleaving does that mean we can assign each core to each EMIF and then we get an effective 64-bit bus that both cores have access to?

 

We have been through the TRM and these answers aren't obvious, and we would appreciate some guidance.

 

Thanks!  Blake

 

  • 0
    TI__Guru**** 393215 points
    The factory team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Genius 9655 points
    You can use a single EMIF interface to support the 2GB DDR. Also, using 2 x16 DDR parts should be fine for this - Basically, you will need 2 8Gbit DDR parts. Do note that we cannot support dual-rank (i.e. configurations that use 2 chip selects). So, you will need to pick a 8 Gbit DDR memory which is a single rank.

    When using a single EMIF, you will have lesser DDR bandwidth vs. using 2 EMIF's. Interleaving is applicable for the 2 EMIF case, that helps reduce DDR page opens/closes, thereby increasing DDR bandwidth. Interleaving is configured to occur at either 128-byte, 256-byte or 512-byte granularity, e.g. If 128-byte granularity interleaving is set, it means first 128-bytes are from EMIF1, second 128-bytes from EMIF2, third 128-bytes from EMIF1 and so on. Interleaving is controlled by the DMM_LISA_MAP register settings.

    Using a single EMIF vs. 2 EMIF's really depends on the system use-case and DDR bandwidth requirements. From a theoretical bandwidth, you get 2x improvement with 2 EMIF's vs. 1 EMIF. Let me know if you have any more follow-up questions.

    Regards, Siva
  • 0 in reply to sivak
    TI__Expert 7245 points

    Hi Siva,

    Great info!  the customer wanted to make absolutely sure of the following, although I suspect it is implied 'yes' by your answer:

    I want to make absolutely sure of the answer to the question of ‘Can you use the dual-core part with a single EMIF?’  I understand the comments and how using two helps with improved bandwidth.  However, we need to know if the internal bus fabric will support the required coherency and data-caching of two cores accessing the same DDR EMIF.  Can you re-ask the question and specify that we need to know if you can successfully use a dual-core solution with a single EMIF?

    Thanks!  Blake

  • 0 in reply to Blake Carpenter
    TI__Genius 9655 points
    Correct. Using 1 EMIF vs. 2 EMIF's should not impact coherency and data-caching.

    Please let us know if you have any further follow-up questions.

    Regards, Siva