Compiler/TMS320C5535: C5535 PLL Configuration crashes the chip and debugger,

Part Number: TMS320C5535

Tool/software: TI C/C++ Compiler

Hi,

I'm trying to configure my PLL by following the documentation. I want to get a clock at 100Mhz, but every time I run it, the debugger and/or the chip crashes as well as CCS. The weird thing is that I can see the clock running on the scope but it's impossible do to anything else. It worked well for a brief period of time but now fails every time. If I don't run the PLL config function the chip seems to run ok around 40MHz and I can debug normally.

I'm on Ubuntu 16.04 with CCSv7, the debugger is the XDS110 and custom hardware.

Here is the init code. all the steps seems to work fine until step #7

Any help is greatly appreciate..

thank you,

~Fabien

CSL_Status pll_config()
{    
    //Init PLL
    //1 - Ensure the clock gen is in bypass mode. clearing the SYSCLKSEL bit
    CSL_SYSCTRL_REGS->CCR2 &= ~CSL_SYS_CCR2_SYSCLKSEL_MASK;    

    //2 - Set CLR_CNTL = 0, bit 15 of CGCR1 register
    CSL_SYSCTRL_REGS->CGCR1 &= ~CSL_SYS_CGCR1_RSVD_MASK;

    //3 -Program RDRATIO:
    // -> M and RDBYPASS in CGCR1 and CGCR2 according to the requirements: M = 796, RDRATIO = 92, RDBYPASS = 0
    CSL_SYSCTRL_REGS->CGCR1 = 0x31C;
    CSL_SYSCTRL_REGS->CGCR2 = 0x2C;

    //4 - Program ODRATIO and OUTDIVEN in CGCR4 ODRATIO = 0, OUTDIVEN = 0
    CSL_SYSCTRL_REGS->CGCR4 = 0;

    //5 - write 0x0806 to the INIT field of CGCR3
    CSL_SYSCTRL_REGS->CGCR3 = 0x0806;

    //6 - set the PLL_PWRDN = 0
    CSL_SYSCTRL_REGS->CGCR1 &= ~CSL_SYS_CGCR1_PLL_PWRDN_MASK;

    //7 - set CLR_CNTL = 1, bit 15 of CGCR1 register
    CSL_SYSCTRL_REGS->CGCR1 |= CSL_SYS_CGCR1_RSVD_MASK;

    //8 - wait 4ms for the PLL to lock
    waitusec(4000);
    
    //9 - place the clock generator in its PLL Mode by setting SYSCLKSEL = 1
    CSL_SYSCTRL_REGS->CCR2 |= CSL_SYS_CCR2_SYSCLKSEL_MASK;

    return CSL_SOK;
}