DRa750: Cache A15 problems

Pawel Sawa

Part Number: DRA750
Other Parts Discussed in Thread: SYSBIOS

Hi

I am developing EMAC driver on DR750 device. I run the driver on M4 and A15 core. It works fine on M4, but on A15.

On A15 I get sometimes incorrect packets. I have pointed out the bug is related with the cache_inv() function call. It works correctly on M4 chip but fails sometimes on A15.

Is there any known bug on A15 Cache, or should there be any extra function calls except Cache_inv()?
Data buffers are aligned to 128bytes.
I the cases I have wrong packets, I see that Cache_inv() does not update cache memory. Both project are the same except of
inclusion of librariies. Project is run under SYSBIOS.

function call:

#include <ti/sysbios/hal/unicache/Cache.h>
Cache_inv( (Ptr)addr, (SizeT)size, (Bits16)Cache_Type_ALL, (Bool)TRUE )

cache config:

/* ================ Cache and MMU configuration ================ */

/* Enable cache */
var Cache = xdc.useModule('ti.sysbios.hal.unicache.Cache');
Cache.enableCache = true;
Cache.maxLineModeBufSize = 64;

/* Use AMMU module */
var AMMU = xdc.useModule('ti.sysbios.hal.ammu.AMMU');

/* Large PAGE */
AMMU.largePages[0].pageEnabled = AMMU.Enable_YES;
AMMU.largePages[0].logicalAddress = 0x40000000;
AMMU.largePages[0].translatedAddress = 0x40000000;
AMMU.largePages[0].translationEnabled = AMMU.Enable_YES;
AMMU.largePages[0].size = AMMU.Large_512M;
AMMU.largePages[0].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.largePages[0].L1_posted = AMMU.PostedPolicy_NON_POSTED;
AMMU.largePages[0].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.largePages[0].L2_posted = AMMU.PostedPolicy_NON_POSTED;

AMMU.largePages[1].pageEnabled = AMMU.Enable_YES;
AMMU.largePages[1].logicalAddress = 0x80000000;
AMMU.largePages[1].translatedAddress = 0x80000000;
AMMU.largePages[1].translationEnabled = AMMU.Enable_YES;
AMMU.largePages[1].size = AMMU.Large_512M;
AMMU.largePages[1].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
AMMU.largePages[1].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
AMMU.largePages[1].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
AMMU.largePages[1].L1_posted = AMMU.PostedPolicy_POSTED;
AMMU.largePages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.largePages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;

AMMU.largePages[2].pageEnabled = AMMU.Enable_YES;
AMMU.largePages[2].logicalAddress = 0xA0000000;
AMMU.largePages[2].translatedAddress = 0xA0000000;
AMMU.largePages[2].translationEnabled = AMMU.Enable_YES;
AMMU.largePages[2].size = AMMU.Large_512M;
AMMU.largePages[2].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.largePages[2].L1_posted = AMMU.PostedPolicy_NON_POSTED;
AMMU.largePages[2].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.largePages[2].L2_posted = AMMU.PostedPolicy_NON_POSTED;

AMMU.largePages[3].pageEnabled = AMMU.Enable_YES;
AMMU.largePages[3].logicalAddress = 0x60000000;
AMMU.largePages[3].translatedAddress = 0x40000000;
AMMU.largePages[3].translationEnabled = AMMU.Enable_YES;
AMMU.largePages[3].size = AMMU.Large_512M;
AMMU.largePages[3].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.largePages[3].L1_posted = AMMU.PostedPolicy_NON_POSTED;
AMMU.largePages[3].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.largePages[3].L2_posted = AMMU.PostedPolicy_NON_POSTED;

/* Medium Page */
AMMU.mediumPages[0].pageEnabled = AMMU.Enable_YES;
AMMU.mediumPages[0].logicalAddress = 0x00300000;
AMMU.mediumPages[0].translatedAddress = 0x40300000;
AMMU.mediumPages[0].translationEnabled = AMMU.Enable_YES;
AMMU.mediumPages[0].size = AMMU.Medium_256K;

AMMU.mediumPages[1].pageEnabled = AMMU.Enable_YES;
AMMU.mediumPages[1].logicalAddress = 0x00400000;
AMMU.mediumPages[1].translatedAddress = 0x40400000;
AMMU.mediumPages[1].translationEnabled = AMMU.Enable_YES;
AMMU.mediumPages[1].size = AMMU.Medium_256K;
AMMU.mediumPages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.mediumPages[1].L1_posted = AMMU.PostedPolicy_POSTED;
AMMU.mediumPages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.mediumPages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;

/* Small Page */
AMMU.smallPages[0].pageEnabled = AMMU.Enable_YES;
AMMU.smallPages[0].logicalAddress = 0x00000000;
AMMU.smallPages[0].translatedAddress = 0x55020000;
AMMU.smallPages[0].translationEnabled = AMMU.Enable_YES;
AMMU.smallPages[0].size = AMMU.Small_16K;
AMMU.smallPages[0].volatileQualifier = AMMU.Volatile_FOLLOW;
AMMU.smallPages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
AMMU.smallPages[0].L1_posted = AMMU.PostedPolicy_NON_POSTED;
AMMU.smallPages[0].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.smallPages[0].L2_posted = AMMU.PostedPolicy_NON_POSTED;

AMMU.smallPages[1].pageEnabled = AMMU.Enable_YES;
AMMU.smallPages[1].logicalAddress = 0x40000000;
AMMU.smallPages[1].translatedAddress = 0x55080000;
AMMU.smallPages[1].translationEnabled = AMMU.Enable_YES;
AMMU.smallPages[1].size = AMMU.Small_16K;
AMMU.smallPages[1].volatileQualifier = AMMU.Volatile_FOLLOW;
AMMU.smallPages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.smallPages[1].L1_posted = AMMU.PostedPolicy_NON_POSTED;
AMMU.smallPages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.smallPages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;

AMMU.smallPages[2].pageEnabled = AMMU.Enable_YES;
AMMU.smallPages[2].logicalAddress = 0x00004000;
AMMU.smallPages[2].translatedAddress = 0x55024000;
AMMU.smallPages[2].translationEnabled = AMMU.Enable_YES;
AMMU.smallPages[2].size = AMMU.Small_16K;
AMMU.smallPages[2].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
AMMU.smallPages[2].L1_posted = AMMU.PostedPolicy_NON_POSTED;
AMMU.smallPages[2].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.smallPages[2].L2_posted = AMMU.PostedPolicy_NON_POSTED;

AMMU.smallPages[3].pageEnabled = AMMU.Enable_YES;
AMMU.smallPages[3].logicalAddress = 0x00008000;
AMMU.smallPages[3].translatedAddress = 0x55028000;
AMMU.smallPages[3].translationEnabled = AMMU.Enable_YES;
AMMU.smallPages[3].size = AMMU.Small_16K;
AMMU.smallPages[3].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.smallPages[3].L1_posted = AMMU.PostedPolicy_NON_POSTED;
AMMU.smallPages[3].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.smallPages[3].L2_posted = AMMU.PostedPolicy_NON_POSTED;

AMMU.smallPages[4].pageEnabled = AMMU.Enable_YES;
AMMU.smallPages[4].logicalAddress = 0x20000000;
AMMU.smallPages[4].translatedAddress = 0x55020000;
AMMU.smallPages[4].translationEnabled = AMMU.Enable_YES;
AMMU.smallPages[4].size = AMMU.Small_16K;
AMMU.smallPages[4].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.smallPages[4].L1_posted = AMMU.PostedPolicy_NON_POSTED;
AMMU.smallPages[4].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.smallPages[4].L2_posted = AMMU.PostedPolicy_NON_POSTED;

A15

Function call:

#include <ti/sysbios/family/arm/a15/Cache.h>
Cache_inv( (Ptr)addr, (SizeT)size_of_packet, (Bits16)Cache_Type_ALL, (Bool)TRUE )

Cache config:

/* ================ Cache and MMU configuration ================ */

var Cache1 = xdc.useModule('ti.sysbios.family.arm.a15.Cache');
Cache1.enableCache = true;
Cache1.errata798870 = true;

/* MMU Configuration */
var Mmu = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');
Mmu.enableMMU = true;

/*
* SYS/BIOS assigns the following defaults to MAIR0 ATTR0, ATTR1 and ATTR2:
*
* ATTR0 -> 0x44 (mark memory region as non-cacheable normal memory)
* ATTR1 -> 0x04 (mark memory region as device memory, i.e. strongly
* ordered and non-cacheable)
* ATTR2 -> 0xFF (mark memory region as normal memory, RW cacheable and
* RW allocate)
*/

/* Descriptor attribute structure */
var attrs0 = new Mmu.DescriptorAttrs();

Mmu.initDescAttrsMeta(attrs0);
attrs0.type = Mmu.DescriptorType_BLOCK; /* BLOCK descriptor */
attrs0.shareable = 2; /* Sharerable */
attrs0.attrIndx = 1; /* Non-cache, device memory */
attrs0.noExecute = true; /* Not executable */

/* Set the descriptor for each entry in the address range */
for (var i=0x40600000; i < 0x60000000; i = i + 0x00200000) {
/* Each 'BLOCK' descriptor entry spans a 2MB address range */
Mmu.setSecondLevelDescMeta(i, i, attrs0);
}

/* Descriptor attribute structure */
var attrs1 = new Mmu.DescriptorAttrs();

Mmu.initDescAttrsMeta(attrs1);
attrs1.type = Mmu.DescriptorType_BLOCK; /* BLOCK descriptor */
attrs1.shareable = 2; /* Sharerable */
attrs1.attrIndx = 2; /* Cached, normal memory */

/* Set the descriptor for each entry in the address range */
for (var i=0x80000000; i < 0xA0000000; i = i + 0x00200000) {
/* Each 'BLOCK' descriptor entry spans a 2MB address range */
Mmu.setSecondLevelDescMeta(i, i, attrs1);
}

Thanks for help
Pawel

over 8 years ago

0 Yordan Kamenov over 8 years ago

TI__Mastermind 42515 points

Hi Pawel,

I am not sure if this is related to your problem, but here is a peculiarity in A15 cache invalidation - it performs write-back before invalidating the cache:
e2e.ti.com/.../508262
downloads.ti.com/.../Cache.html

Can you clarify which version is the SDK you use?

Regards,
Yordan

0 Yordan Kamenov over 8 years ago in reply to Yordan Kamenov

TI__Mastermind 42515 points

Hi Pawel,

I haven't heard back from you, I'm assuming you were able to resolve your issue.
If not, just post a reply below (or create a new thread if the thread has locked due to time-out).

Regards,
Yordan

0 Pawel Sawa over 8 years ago in reply to Yordan Kamenov

Prodigy 150 points

Hi Yordan,

The problem was Cache validation. As invalidate and write back works the same, it is needed to write back buffer before giving it to DMA receive transfer and than invalidate it after receive.
If you do not do it, it will overwrite cache data over received data.

Thanks,
Pawel

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DRa750: Cache A15 problems