For posted WRITE operations (e.g. NWRITE and SWRITE transactions) that do not require a RapidIO response packet, I would like to know more about when the peripheral sets the completion code status register and appropriate interrupt bit of the ICSR. It is described as follows in the User's Guide (SPRUGW1B).
Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. B)
http://www.ti.com/lit/ug/sprugw1b/sprugw1b.pdf
2.3.2.2.1 WRITE Transactions (Page 61)
"For posted WRITE operations that do not require a RapidIO response packet, a core
may submit multiple outstanding requests. For instance, a single core may have many
streaming write packets buffered at any given time, given out-going resources. In this
application, the LSU can be released to the shadow registers as soon as the packet is
written into the shared TX buffer pool. If the request has been flow controlled, the
peripheral will set the completion code status register and appropriate interrupt bit of
the ICSR. The control/command registers can be released after the interrupt service
routine completes."
In the transaction that spans multiple packets, when the peripheral sets the completion code status register and appropriate interrupt bit of the ICSR, has the acknowledge control symbol for the last packet been received? Or has only the acknowledge control symbol for the first packet been received?
Best regards,
Daisuke
