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RTOS/AM3358: NIMU integration

Part Number: AM3358
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

Good day,

I have taken the example program "NIMU_BasicExample_bbbAM335x_armExampleproject" and trimmed it down so I send myself a nice "hello" over TCP port 7 and it works great.  

I have a separate program running that I am reading sensor data off of the SPI1 bus based on the "MCSPI_SlaveMode_MasterExample_bbbAM335x_armExampleProject" and that works great.

I am running into issues when trying to integrate what is working in my NIMU example into my SPI example. 

I actually have the combined project compiling without warning or error and it downloads to by BBB.  The issue is that when it tries to run, it says that it can't open the socket and the whole thing crashes.  I have actually taken all of my networking code out of the program and the program still crashes.

Here is my working NIMU code for reference and what I tried to put in my SPI code:

/*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/

/* ========================================================================== */
/* Include Files */
/* ========================================================================== */

#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <xdc/std.h>
#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/family/arm/a8/Mmu.h>

#include <ti/ndk/inc/stkmain.h>

#include <ti/drv/emac/emac_drv.h>
#include <ti/drv/emac/src/v4/emac_drv_v4.h>

#include <ti/starterware/include/types.h>
#include <ti/starterware/include/hw/hw_types.h>
#include <ti/starterware/include/hw/hw_control_am335x.h>
#include <ti/starterware/include/hw/soc_am335x.h>
#include <ti/starterware/include/ethernet.h>
#include <ti/starterware/include/soc_control.h>

#include <ti/board/board.h>

/* UART Header files */
#include <ti/drv/uart/UART.h>
#include <ti/drv/uart/UART_stdio.h>

#include <ti/ndk/inc/nettools/inc/inet.h>

extern char *LocalIPAddr;

/* Enable the below macro to have prints on the IO Console */
//#define IO_CONSOLE


#ifndef IO_CONSOLE
#define NIMU_log UART_printf
#else
#define NIMU_log printf
#endif

/* ========================================================================== */
/* Macros */
/* ========================================================================== */

/**Phy address of the CPSW port 1*/
#define EMAC_CPSW_PORT0_PHY_ADDR_EVM 0
/**Phy address of the CPSW port 1*/
#define EMAC_CPSW_PORT1_PHY_ADDR_EVM 1


#define MAX_TABLE_ENTRIES 3

/* ========================================================================== */
/* Global Variables */
/* ========================================================================== */


/**Task handle for EIP*/
Task_Handle main_task;

static int nimu_device_index = 0U;


NIMU_DEVICE_TABLE_ENTRY NIMUDeviceTable[MAX_TABLE_ENTRIES];

void TaskFxn(UArg a0, UArg a1);
extern int CpswEmacInit (STKEVENT_Handle hEvent);


/**
* \name main
* \brief Main Function
* \param none
* \return none
*
*/
int main()
{
/* Call board init functions */
Board_initCfg boardCfg;
Task_Params taskParams;
EMAC_HwAttrs_V4 cfg;

boardCfg = BOARD_INIT_PINMUX_CONFIG |
BOARD_INIT_MODULE_CLOCK | BOARD_INIT_UART_STDIO;
Board_init(boardCfg);

/* Chip configuration MII/RMII selection */
SOCCtrlCpswPortMacModeSelect(1, ETHERNET_MAC_TYPE_MII);
SOCCtrlCpswPortMacModeSelect(2, ETHERNET_MAC_TYPE_MII);

EMAC_socGetInitCfg(0, &cfg);
cfg.port[0].phy_addr = EMAC_CPSW_PORT0_PHY_ADDR_EVM;
cfg.port[1].phy_addr = EMAC_CPSW_PORT0_PHY_ADDR_EVM;
cfg.macModeFlags = EMAC_CPSW_CONFIG_MODEFLG_FULLDUPLEX;
EMAC_socSetInitCfg(0, &cfg);

Task_Params_init(&taskParams);
taskParams.priority = 1;
taskParams.stackSize = 0x1400;
main_task = Task_create (TaskFxn, &taskParams, NULL);

NIMUDeviceTable[nimu_device_index++].init = &CpswEmacInit ;
NIMUDeviceTable[nimu_device_index].init = NULL ;

BIOS_start();

return -1;
}

/**
* \name TaskFxn
* \brief Task which do EIP initialization
* \param a0
* \param a1
* \return none
*
*/
void TaskFxn(UArg a0, UArg a1)
{
NIMU_log("\n\rSYS/BIOS Ethernet/IP (CPSW) Sample application, EVM IP address: %s\n\r", LocalIPAddr);

SOCKET s = INVALID_SOCKET;
struct sockaddr_in sin1;
char *pBuf = 0;
struct timeval timeout;

// Allocate the file descriptor environment for this Task
fdOpenSession( (HANDLE)Task_self() );
printf("\n== Start TCP Echo Client Test ==\n");

// Create test socket
s = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP);
if( s == INVALID_SOCKET )
{
printf("failed socket create (%d)\n",fdError());
goto leave;
}
else{
printf("created socket\n");
}
char *IPAddr = "192.168.1.6";
// Prepare address for connect
bzero( &sin1, sizeof(struct sockaddr_in) );
sin1.sin_family = AF_INET;
sin1.sin_addr.s_addr = inet_addr(IPAddr);
sin1.sin_port = htons(7);

// Configure our Tx and Rx timeout to be 5 seconds
timeout.tv_sec = 5;
timeout.tv_usec = 0;
setsockopt( s, SOL_SOCKET, SO_SNDTIMEO, &timeout, sizeof( timeout ) );
setsockopt( s, SOL_SOCKET, SO_RCVTIMEO, &timeout, sizeof( timeout ) );

// Connect socket
if( connect( s, (PSA) &sin1, sizeof(sin1) ) < 0 )
{
printf("failed connect (%d)\n",fdError());
goto leave;
}
else{
printf("connected\n");
}

// Allocate a working buffer
if( !(pBuf = malloc( 4096 )) )
{
printf("failed temp buffer allocation\n");
goto leave;
}

// Fill buffer with a test pattern
// for(i=0; i<4096; i++)
*(pBuf+0) = (char)'h';
*(pBuf+1) = (char)'e';
*(pBuf+2) = (char)'l';
*(pBuf+3) = (char)'l';
*(pBuf+4) = (char)'o';


// Send the buffer
if( send( s, pBuf, 5, 0 ) < 0 )
{
printf("send failed (%d)\n",fdError());
goto leave;
}
else{
printf("sent\n");
}


leave:
if( pBuf )
free( pBuf );

if( s != INVALID_SOCKET )
fdClose( s );

printf("== End TCP Echo Client Test ==\n\n");

// Free the file descriptor environment for this Task
fdCloseSession( (HANDLE)Task_self() );

#ifdef NIMU_FTP_APP
ftpserver_init();
#endif
}

  • The RTOS team have been notified. They will respond here.
  • Hi Alex,

    Have you merged .cfg file to allocate proper stack/heap size and manage cacheability of memory?

    These tips may help resolve the crash issue you observed:
    processors.wiki.ti.com/.../Processor_SDK_RTOS:_TI_RTOS_Tips_And_Tricks
    processors.wiki.ti.com/.../Processor_SDK_RTOS:_TI_RTOS_Tips_And_Tricks

    Regards,
    Garrett
  • Here is my .cfg file. I have a crazy amount of heap and stack for some other reasons so that shouldn't be the problem.

    Ignore my UIA stuff I have commented out - that is a different issue.

    /**
    * \file spi_arm_bbbAM335x_slavemode.cfg
    *
    * \brief Sysbios config file for MCSPI example project on AM335X BBB EVM.
    *
    */

    /*
    * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
    *
    * Redistribution and use in source and binary forms, with or without
    * modification, are permitted provided that the following conditions
    * are met:
    *
    * Redistributions of source code must retain the above copyright
    * notice, this list of conditions and the following disclaimer.
    *
    * Redistributions in binary form must reproduce the above copyright
    * notice, this list of conditions and the following disclaimer in the
    * documentation and/or other materials provided with the
    * distribution.
    *
    * Neither the name of Texas Instruments Incorporated nor the names of
    * its contributors may be used to endorse or promote products derived
    * from this software without specific prior written permission.
    *
    * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
    * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
    * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
    * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
    * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
    * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
    * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
    * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    *
    */
    /* ================ General configuration ================ */
    var Defaults = xdc.useModule('xdc.runtime.Defaults');
    var Diags = xdc.useModule('xdc.runtime.Diags');
    var Error = xdc.useModule('xdc.runtime.Error');
    var Main = xdc.useModule('xdc.runtime.Main');
    var Memory = xdc.useModule('xdc.runtime.Memory')
    var SysMin = xdc.useModule('xdc.runtime.SysMin');
    var System = xdc.useModule('xdc.runtime.System');
    var Text = xdc.useModule('xdc.runtime.Text');
    var Clock = xdc.useModule('ti.sysbios.knl.Clock');
    var Swi = xdc.useModule('ti.sysbios.knl.Swi');
    var Task = xdc.useModule('ti.sysbios.knl.Task');
    var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
    var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
    var Timer = xdc.useModule('ti.sysbios.hal.Timer');
    var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
    var SemihostSupport = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport');
    var Global = xdc.useModule('ti.ndk.config.Global');
    //var Log = xdc.useModule('xdc.runtime.Log');
    //var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');

    var Global = xdc.useModule('ti.ndk.config.Global');
    var Tcp = xdc.useModule('ti.ndk.config.Tcp');
    var Ip = xdc.useModule('ti.ndk.config.Ip');

    /*
    * Program.argSize sets the size of the .args section.
    * The examples don't use command line args so argSize is set to 0.
    */
    Program.argSize = 0x0;


    /* System stack size (used by ISRs and Swis) */
    Program.stack = 6000000;

    /*
    * Uncomment this line to globally disable Asserts.
    * All modules inherit the default from the 'Defaults' module. You
    * can override these defaults on a per-module basis using Module.common$.
    * Disabling Asserts will save code space and improve runtime performance.
    Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
    */
    Defaults.common$.diags_ASSERT = Diags.ALWAYS_ON;

    /*
    * Uncomment this line to keep module names from being loaded on the target.
    * The module name strings are placed in the .const section. Setting this
    * parameter to false will save space in the .const section. Error and
    * Assert messages will contain an "unknown module" prefix instead
    * of the actual module name.
    Defaults.common$.namedModule = false;
    */
    Defaults.common$.namedModule = false;

    /*
    * Minimize exit handler array in System. The System module includes
    * an array of functions that are registered with System_atexit() to be
    * called by System_exit().
    */
    System.maxAtexitHandlers = 4;

    /*
    * Uncomment this line to disable the Error print function.
    * We lose error information when this is disabled since the errors are
    * not printed. Disabling the raiseHook will save some code space if
    * your app is not using System_printf() since the Error_print() function
    * calls System_printf().
    Error.raiseHook = null;
    */
    Error.raiseHook = null;
    /*
    * Uncomment this line to keep Error, Assert, and Log strings from being
    * loaded on the target. These strings are placed in the .const section.
    * Setting this parameter to false will save space in the .const section.
    * Error, Assert and Log message will print raw ids and args instead of
    * a formatted message.
    Text.isLoaded = false;
    */
    Text.isLoaded = false;
    /*
    * Uncomment this line to disable the output of characters by SysMin
    * when the program exits. SysMin writes characters to a circular buffer.
    * This buffer can be viewed using the SysMin Output view in ROV.
    */
    SysMin.flushAtExit = false;

    /*
    * Create and install logger for the whole system
    */

    //var loggerBufParams = new LoggerBuf.Params();
    //loggerBufParams.numEntries = 32;
    //var logger0 = LoggerBuf.create(loggerBufParams);
    //Defaults.common$.logger = logger0;
    //Main.common$.diags_INFO = Diags.ALWAYS_ON;

    System.SupportProxy = SysMin;




    var Global = xdc.useModule('ti.ndk.config.Global');
    var Ip = xdc.useModule('ti.ndk.config.Ip');

    Global.netSchedulerPri = Global.NC_PRIORITY_HIGH;
    Global.debugAbortLevel = Global.DBG_ERROR;
    Global.debugPrintLevel = Global.DBG_NONE;

    var ti_sysbios_hal_Timer = xdc.useModule('ti.sysbios.hal.Timer');
    /*
    /* Global.stackThreadUser = "&NDKACD_stackThread"; */

    var Tcp = xdc.useModule('ti.ndk.config.Tcp');
    var Udp = xdc.useModule('ti.ndk.config.Udp');
    /*
    /* Settings for static IP configuration */

    Ip.ResolveIP = false;
    Ip.CallByIP = false;
    Ip.autoIp = false;
    Ip.address = "192.168.1.4";
    Ip.mask = "255.255.255.0";
    Ip.gatewayIpAddr = "192.168.1.1";


    Global.ndkTickPeriod = 200;
    Global.kernTaskPriLevel = 11;
    Global.serviceReportHook = null;
    Global.IPv6 = false;
    Global.pktNumFrameBufs=384;

    Tcp.transmitBufSize = 16384;
    Tcp.receiveBufSize = 65536;
    Tcp.receiveBufLimit = 65536;


    /*
    * Create and install logger for the whole system
    */
    /* ================ BIOS configuration ================ */

    var BIOS = xdc.useModule('ti.sysbios.BIOS');
    BIOS.libType = BIOS.LibType_Custom;
    BIOS.customCCOpts = BIOS.customCCOpts.replace(" -g ","");
    BIOS.assertsEnabled = true;
    //BIOS.logsEnabled = true;
    BIOS.swiEnabled = true;
    /*
    * The BIOS module will create the default heap for the system.
    * Specify the size of this default heap.
    */
    BIOS.heapSize = 6000000;

    Swi.common$.namedInstance = true;
    Program.sectionsExclude = ".*";

    Clock.tickPeriod = 1000;
    Hwi.dispatcherSwiSupport = true;
    Hwi.dispatcherTaskSupport = true;
    Hwi.dispatcherAutoNestingSupport = true;

    Task.enableIdleTask = true;
    Task.initStackFlag = true;
    Task.checkStackFlag = true;

    /* ================ Driver configuration ================ */

    /* Load the Osal package */
    var osType = "tirtos";
    var Osal = xdc.loadPackage('ti.osal');
    Osal.Settings.osType = osType;

    /*use CSL package*/
    var socType = "am335x";
    var Csl = xdc.loadPackage('ti.csl');
    Csl.Settings.deviceType = socType;

    /* Load the spi package */
    var Spi = xdc.loadPackage('ti.drv.spi');
    Spi.Settings.socType = socType;

    /* Load the I2C package */
    var socType = "am335x";
    var I2C = xdc.loadPackage('ti.drv.i2c');
    I2C.Settings.socType = socType;

    /* Load the board package */
    var Board = xdc.loadPackage('ti.board');
    Board.Settings.boardName = "bbbAM335x";

    /* Load the uart package */
    var socType = "am335x";
    var Uart = xdc.loadPackage('ti.drv.uart');
    Uart.Settings.socType = socType;

    /* Load the EMAC packages */
    var Emac = xdc.loadPackage('ti.drv.emac');
    Emac.Settings.socType = socType;

    /* Load the NIMU package */
    var Nimu = xdc.loadPackage('ti.transport.ndk.nimu');
    Nimu.Settings.socType = socType;

    /* ================ Cache and MMU configuration ================ */

    var Cache = xdc.useModule('ti.sysbios.family.arm.a8.Cache');
    Cache.enableCache = false;

    var Mmu = xdc.useModule('ti.sysbios.family.arm.a8.Mmu');
    Mmu.enableMMU = true;

    /* Force peripheral section to be NON cacheable strongly-ordered memory */
    var peripheralAttrs = {
    type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
    tex: 0,
    bufferable : false, // bufferable
    cacheable : false, // cacheable
    shareable : false, // shareable
    noexecute : true, // not executable
    };

    /* Define the base address of the 1 Meg page the peripheral resides in. */
    var peripheralBaseAddr = 0x44e00400;;

    /* Configure the corresponding MMU page descriptor accordingly */
    Mmu.setFirstLevelDescMeta(peripheralBaseAddr,
    peripheralBaseAddr,
    peripheralAttrs);


    /* Define the base address of the 1 Meg page the peripheral resides in. */
    var peripheralBaseAddr = 0x481a6000;

    /* Configure the corresponding MMU page descriptor accordingly */
    Mmu.setFirstLevelDescMeta(peripheralBaseAddr,
    peripheralBaseAddr,
    peripheralAttrs);
    var hwi0Params = new Hwi.Params();
    hwi0Params.instance.name = "gpio1int";
    Program.global.gpio1int = Hwi.create(98, "&gpio1intFunction", hwi0Params);
    var semaphore0Params = new Semaphore.Params();
    semaphore0Params.instance.name = "BMI160Sem";
    semaphore0Params.mode = Semaphore.Mode_BINARY;
    Program.global.BMI160Sem = Semaphore.create(0, semaphore0Params);
    var task0Params = new Task.Params();
    task0Params.instance.name = "bmi160task";
    task0Params.priority = 9;
    task0Params.stackSize = 4000000;
    Program.global.bmi160task = Task.create("&readBMI160", task0Params);
    Task.idleTaskStackSize = 4000000;
    Task.defaultStackSize = 4000000;
    var clock0Params = new Clock.Params();
    clock0Params.instance.name = "clock1000ms";
    clock0Params.period = 1000;
    clock0Params.startFlag = true;
    Program.global.clock1000ms = Clock.create("&clock1hz", 1000, clock0Params);
    var semaphore1Params = new Semaphore.Params();
    semaphore1Params.instance.name = "oneHzsem";
    semaphore1Params.mode = Semaphore.Mode_COUNTING;
    Program.global.oneHzsem = Semaphore.create(null, semaphore1Params);
    var task1Params = new Task.Params();
    task1Params.instance.name = "onehztask";
    task1Params.priority = 3;
    task1Params.stackSize = 4000000;
    Program.global.onehztask = Task.create("&oneHzTask", task1Params);
    Defaults.common$.diags_INTERNAL = Diags.ALWAYS_ON;
    var task2Params = new Task.Params();
    task2Params.instance.name = "hundredhztask";
    task2Params.priority = 5;
    task2Params.stackSize = 4000000;
    task2Params.stack = null;
    Program.global.hundredhztask = Task.create("&hundredHzTask", task2Params);
    var semaphore2Params = new Semaphore.Params();
    semaphore2Params.instance.name = "hundredHzsem";
    semaphore2Params.mode = Semaphore.Mode_COUNTING;
    Program.global.hundredHzsem = Semaphore.create(null, semaphore2Params);
    var clock1Params = new Clock.Params();
    clock1Params.instance.name = "clock10ms";
    clock1Params.period = 10;
    clock1Params.startFlag = true;
    Program.global.clock10ms = Clock.create("&clock100hz", 10, clock1Params);
    BIOS.heapTrackEnabled = true;
  • Alex,

    >>I have actually taken all of my networking code out of the program and the program still crashes.
    What was the crash log (stack trace, register dump) look like when it crashes?

    Regards,
    Garrett
  • Here you go.

    521177 12
    R PC 0x0000000B 0x8008C8C0
    R SP 0x0000000B 0x4030CAC4
    R LR 0x0000000B 0x8008C8C0
    R CPSR 0x0000000B 0x60000197
    R R0 0x0000000B 0x00000018
    R R1 0x0000000B 0x00020023
    R R2 0x0000000B 0x00000006
    R R3 0x0000000B 0x00000000
    R R4 0x0000000B 0x00000018
    R R5 0x0000000B 0x00020023
    R R6 0x0000000B 0x00000000
    R R7 0x0000000B 0x00000000
    R R8 0x0000000B 0x00000037
    R R9 0x0000000B 0x000000CD
    R R10 0x0000000B 0x81A714D0
    R R11 0x0000000B 0x80CBACAC
    R R12 0x0000000B 0x20000197
    R R13 0x0000000B 0x4030CAC4
    R R14 0x0000000B 0x8008C8C0
    R USER_Registers_R8_USER 0x0000000B 0x00000037
    R USER_Registers_R9_USER 0x0000000B 0x000000CD
    R USER_Registers_R10_USER 0x0000000B 0x81A714D0
    R USER_Registers_R11_USER 0x0000000B 0x80CBACAC
    R USER_Registers_R12_USER 0x0000000B 0x20000197
    R USER_Registers_R13_USER 0x0000000B 0x80CBAB80
    R USER_Registers_R14_USER 0x0000000B 0x81A714D0
    R FIQ_Registers_SPSR_FIQ 0x0000000B 0x00000000
    R FIQ_Registers_R8_FIQ 0x0000000B 0xCB8AF62B
    R FIQ_Registers_R9_FIQ 0x0000000B 0x4FB466FF
    R FIQ_Registers_R10_FIQ 0x0000000B 0xA6733716
    R FIQ_Registers_R11_FIQ 0x0000000B 0x90448284
    R FIQ_Registers_R12_FIQ 0x0000000B 0x2000019F
    R FIQ_Registers_R13_FIQ 0x0000000B 0x814B80F8
    R FIQ_Registers_R14_FIQ 0x0000000B 0x00000000
    R Supervisor_Registers_SPSR_SVC 0x0000000B 0x60000197
    R Supervisor_Registers_R13_SVC 0x0000000B 0x4030CAC4
    R Supervisor_Registers_R14_SVC 0x0000000B 0x8008C8C0
    R Abort_Registers_SPSR_ABT 0x0000000B 0x6000011F
    R Abort_Registers_R13_ABT 0x0000000B 0x81A70CB0
    R Abort_Registers_R14_ABT 0x0000000B 0x80086EB4
    R IRQ_Registers_SPSR_IRQ 0x0000000B 0x2000011F
    R IRQ_Registers_R13_IRQ 0x0000000B 0xC08D4380
    R IRQ_Registers_R14_IRQ 0x0000000B 0x80086AF8
    R Undefined_Registers_SPSR_UND 0x0000000B 0x00000000
    R Undefined_Registers_R13_UND 0x0000000B 0x81A70E78
    R Undefined_Registers_R14_UND 0x0000000B 0xC04D6E41
    R All_Banked_Registers_SPSR_FIQ 0x0000000B 0x00000000
    R All_Banked_Registers_R8_FIQ 0x0000000B 0xCB8AF62B
    R All_Banked_Registers_R9_FIQ 0x0000000B 0x4FB466FF
    R All_Banked_Registers_R10_FIQ 0x0000000B 0xA6733716
    R All_Banked_Registers_R11_FIQ 0x0000000B 0x90448284
    R All_Banked_Registers_R12_FIQ 0x0000000B 0x2000019F
    R All_Banked_Registers_R13_FIQ 0x0000000B 0x814B80F8
    R All_Banked_Registers_R14_FIQ 0x0000000B 0x00000000
    R All_Banked_Registers_SPSR_SVC 0x0000000B 0x60000197
    R All_Banked_Registers_R13_SVC 0x0000000B 0x4030CAC4
    R All_Banked_Registers_R14_SVC 0x0000000B 0x8008C8C0
    R All_Banked_Registers_SPSR_ABT 0x0000000B 0x6000011F
    R All_Banked_Registers_R13_ABT 0x0000000B 0x81A70CB0
    R All_Banked_Registers_R14_ABT 0x0000000B 0x80086EB4
    R All_Banked_Registers_SPSR_IRQ 0x0000000B 0x2000011F
    R All_Banked_Registers_R13_IRQ 0x0000000B 0xC08D4380
    R All_Banked_Registers_R14_IRQ 0x0000000B 0x80086AF8
    R All_Banked_Registers_SPSR_UND 0x0000000B 0x00000000
    R All_Banked_Registers_R13_UND 0x0000000B 0x81A70E78
    R All_Banked_Registers_R14_UND 0x0000000B 0xC04D6E41
    R CP14_Registers_CP14_DEBUG_ID 0x0000000B 0x15141032
    R CP14_Registers_CP14_DEBUG_ROM_ADDRESS 0x0000000B 0x00000000
    R CP14_Registers_CP14_DEBUG_SELF_ADDRESS_OFFSET 0x0000000B 0x00000000
    R CP14_Registers_CP14_DATA_TRANSFER 0x0000000B 0x00C50879
    R CP14_Registers_CP14_DEBUG_STATUS_AND_CONTROL 0x0000000B 0x020F680F
    R CP15_Registers_CP15_ID_CODE 0x0000000B 0x413FC082
    R CP15_Registers_CP15_PROCESSOR_FEATURE_0 0x0000000B 0x00001131
    R CP15_Registers_CP15_PROCESSOR_FEATURE_1 0x0000000B 0x00000011
    R CP15_Registers_CP15_DEBUG_FEATURE_0 0x0000000B 0x00010400
    R CP15_Registers_CP15_AUXILIARY_FEATURE_0 0x0000000B 0x00000000
    R CP15_Registers_CP15_MEMORY_MODEL_FEATURE_0 0x0000000B 0x01100003
    R CP15_Registers_CP15_MEMORY_MODEL_FEATURE_1 0x0000000B 0x20000000
    R CP15_Registers_CP15_MEMORY_MODEL_FEATURE_2 0x0000000B 0x01202000
    R CP15_Registers_CP15_MEMORY_MODEL_FEATURE_3 0x0000000B 0x00000211
    R CP15_Registers_CP15_INSTRUCTION_SET_ATTRIBUTE_0 0x0000000B 0x00101111
    R CP15_Registers_CP15_INSTRUCTION_SET_ATTRIBUTE_1 0x0000000B 0x13112111
    R CP15_Registers_CP15_INSTRUCTION_SET_ATTRIBUTE_2 0x0000000B 0x21232031
    R CP15_Registers_CP15_INSTRUCTION_SET_ATTRIBUTE_3 0x0000000B 0x11112131
    R CP15_Registers_CP15_INSTRUCTION_SET_ATTRIBUTE_4 0x0000000B 0x00011142
    R CP15_Registers_CP15_INSTRUCTION_SET_ATTRIBUTE_5 0x0000000B 0x00000000
    R CP15_Registers_CP15_INSTRUCTION_SET_ATTRIBUTE_6 0x0000000B 0x00000000
    R CP15_Registers_CP15_INSTRUCTION_SET_ATTRIBUTE_7 0x0000000B 0x00000000
    R CP15_Registers_CP15_CONTROL_REGISTER 0x0000000B 0x00C50879
    R CP15_Registers_CP15_AUXILIARY_CONTROL 0x0000000B 0x00000042
    R CP15_Registers_CP15_COPROCESSOR_ACCESS_CONTROL 0x0000000B 0x00F00000
    R CP15_Registers_CP15_SECURE_CONFIGURATION 0x0000000B 0x00F00000
    R CP15_Registers_CP15_SECURE_DEBUG_ENABLE 0x0000000B 0x00F00000
    R CP15_Registers_CP15_NON_SECURE_ACCESS_CONTROL 0x0000000B 0x00070C00
    R CP15_Registers_CP15_VECTOR_BASE_ADDRESS 0x0000000B 0x80091400
    R CP15_Registers_CP15_MONITOR_VECTOR_BASE_ADDRESS 0x0000000B 0x80091400
    R CP15_Registers_CP15_INTERRUPT_STATUS 0x0000000B 0x00000080
    R CP15_Registers_CP15_MMU_TLB_TYPE 0x0000000B 0x00202001
    R CP15_Registers_CP15_MMU_XLATION_TABLE_BASE_0 0x0000000B 0x800A0000
    R CP15_Registers_CP15_MMU_XLATION_TABLE_BASE_1 0x0000000B 0x00000000
    R CP15_Registers_CP15_MMU_XLATION_TABLE_BASE_CONTROL 0x0000000B 0x00000000
    R CP15_Registers_CP15_MMU_DOMAIN_ACCESS_CONTROL 0x0000000B 0x55555555
    R CP15_Registers_CP15_DATA_FAULT_STATUS 0x0000000B 0x00000005
    R CP15_Registers_CP15_INSTRUCTION_FAULT_STATUS 0x0000000B 0x00000000
    R CP15_Registers_CP15_MMU_DATA_AUXILIARY_FAULT_STATUS 0x0000000B 0x00000000
    R CP15_Registers_CP15_MMU_INSTR_AUXILIARY_FAULT_STATUS 0x0000000B 0x00000000
    R CP15_Registers_CP15_DATA_FAULT_ADDRESS 0x0000000B 0x4A10081C
    R CP15_Registers_CP15_INSTRUCTION_FAULT_ADDRESS 0x0000000B 0x00000000
    R CP15_Registers_CP15_MMU_TLB_DATA_LOCKDOWN 0x0000000B 0x15800000
    R CP15_Registers_CP15_MMU_TLB_INSTR_LOCKDOWN 0x0000000B 0x10C00000
    R CP15_Registers_CP15_MMU_PRIMARY_REGION_REMAP 0x0000000B 0x00098AA4
    R CP15_Registers_CP15_MMU_NORMAL_MEMORY_REMAP 0x0000000B 0x44E048E0
    R CP15_Registers_CP15_MMU_FCSE_PID 0x0000000B 0x00000000
    R CP15_Registers_CP15_MMU_CONTEXT_ID 0x0000000B 0x00000000
    R CP15_Registers_CP15_MMU_THREAD_PROCESS_READ_WRITE_ID 0x0000000B 0x00000000
    R CP15_Registers_CP15_MMU_THREAD_PROCESS_READ_ONLY_ID 0x0000000B 0x00000000
    R CP15_Registers_CP15_MMU_THREAD_PROCESS_PRIV_ONLY_ID 0x0000000B 0x00000000
    R CP15_Registers_CP15_MMU_PERIPHERAL_PORT_MEMORY_REMAP 0x0000000B 0x00000000
    R CP15_Registers_CP15_MMU_TLB_LOCKDOWN_INDEX 0x0000000B 0x00000000
    R CP15_Registers_CP15_MMU_TLB_LOCKDOWN_VA 0x0000000B 0x00000000
    R CP15_Registers_CP15_MMU_TLB_LOCKDOWN_PA 0x0000000B 0x00000000
    R CP15_Registers_CP15_MMU_TLB_LOCKDOWN_ATTRIBUTES 0x0000000B 0x00000000
    R CP15_Registers_CP15_CACHE_TYPE 0x0000000B 0x82048004
    R CP15_Registers_CP15_CURRENT_CACHE_LEVEL_ID 0x0000000B 0x0A000023
    R CP15_Registers_CP15_CURRENT_CACHE_SIZE_ID 0x0000000B 0xE00FE01A
    R CP15_Registers_CP15_CACHE_SIZE_SELECTION 0x0000000B 0x00000000
    R CP15_Registers_CP15_PA 0x0000000B 0x00000000
    R CP15_Registers_CP15_PA_SUPERSECTION_SUPPORT 0x0000000B 0x00000000
    R CP15_Registers_CP15_L2_DCACHE_LOCKDOWN 0x0000000B 0x00000000
    R CP15_Registers_CP15_L2_ICACHE_LOCKDOWN 0x0000000B 0x00000000
    R CP15_Registers_CP15_L2_AUXILIARY_CONTROL 0x0000000B 0x00000042
    R CP15_Registers_CP15_DMA_ID_STATUS_PRESENT 0x0000000B 0x00000003
    R CP15_Registers_CP15_DMA_ID_STATUS_QUEUED 0x0000000B 0x00000000
    R CP15_Registers_CP15_DMA_ID_STATUS_RUNNING 0x0000000B 0x00000000
    R CP15_Registers_CP15_DMA_ID_STATUS_INTERRUPT 0x0000000B 0x00000000
    R CP15_Registers_CP15_DMA_USER_ACCESSIBILITY 0x0000000B 0x00000000
    R CP15_Registers_CP15_DMA_CHANNEL_NUMBER 0x0000000B 0x00000000
    R CP15_Registers_CP15_DMA_CONTROL 0x0000000B 0x04000000
    R CP15_Registers_CP15_DMA_INT_START_ADDRESS 0x0000000B 0x00000000
    R CP15_Registers_CP15_DMA_EXT_START_ADDRESS 0x0000000B 0x00000000
    R CP15_Registers_CP15_DMA_INT_END_ADDRESS 0x0000000B 0x00000000
    R CP15_Registers_CP15_DMA_CHANNEL_STATUS 0x0000000B 0x00000000
    R CP15_Registers_CP15_DMA_CONTEXT_ID 0x0000000B 0x00000000
    R CP15_Registers_CP15_DATA_L1_HIGH 0x0000000B 0x00000000
    R CP15_Registers_CP15_DATA_L1_LOW 0x0000000B 0x00000000
    R CP15_Registers_CP15_INSTR_L1_HIGH 0x0000000B 0x00C50879
    R CP15_Registers_CP15_INSTR_L1_LOW 0x0000000B 0x00C50879
    R CP15_Registers_CP15_L2_R2 0x0000000B 0x00C50879
    R CP15_Registers_CP15_L2_R1 0x0000000B 0x00C50879
    R CP15_Registers_CP15_L2_R0 0x0000000B 0x00C50879
    R CP15_Registers_CP15_PERFORMANCE_MONITOR_CONTROL 0x0000000B 0x41002001
    R CP15_Registers_CP15_COUNT_ENABLE_SET 0x0000000B 0x80000000
    R CP15_Registers_CP15_COUNT_ENABLE_CLEAR 0x0000000B 0x80000000
    R CP15_Registers_CP15_OVERFLOW_FLAG_STATUS 0x0000000B 0x00000000
    R CP15_Registers_CP15_SOFTWARE_INCREMENT 0x0000000B 0x00000000
    R CP15_Registers_CP15_COUNTER_SELECTION 0x0000000B 0x00000000
    R CP15_Registers_CP15_CYCLE_COUNT 0x0000000B 0x30D16FDA
    R CP15_Registers_CP15_EVENT_SELECTION 0x0000000B 0x00000000
    R CP15_Registers_CP15_PERFORMANCE_MONITOR_COUNT 0x0000000B 0x00000000
    R CP15_Registers_CP15_USER_ENABLE 0x0000000B 0x00000000
    R CP15_Registers_CP15_INTERRUPT_ENABLE_SET 0x0000000B 0x00000000
    R CP15_Registers_CP15_INTERRUPT_ENABLE_CLEAR 0x0000000B 0x00000000
    R CM_PER_CM_PER_L4LS_CLKSTCTRL 0x0000000B 0x02004102
    R CM_PER_CM_PER_L3S_CLKSTCTRL 0x0000000B 0x0000000A
    R CM_PER_CM_PER_L4FW_CLKSTCTRL 0x0000000B 0x00000102
    R CM_PER_CM_PER_L3_CLKSTCTRL 0x0000000B 0x0000005E
    R CM_PER_CM_PER_CPGMAC0_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_LCDC_CLKCTRL 0x0000000B 0x00070000
    R CM_PER_CM_PER_USB0_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_TPTC0_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_EMIF_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_OCMCRAM_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_GPMC_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_MCASP0_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_UART5_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_MMC0_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_ELM_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_I2C2_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_I2C1_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_SPI0_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_SPI1_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_L4LS_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_L4FW_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_MCASP1_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_UART1_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_UART2_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_UART3_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_UART4_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_TIMER7_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_TIMER2_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_TIMER3_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_TIMER4_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_GPIO1_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_GPIO2_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_GPIO3_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_TPCC_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_DCAN0_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_DCAN1_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_EPWMSS1_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_EMIF_FW_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_EPWMSS0_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_EPWMSS2_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_L3_INSTR_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_L3_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_IEEE5000_CLKCTRL 0x0000000B 0x00040002
    R CM_PER_CM_PER_PRU_ICSS_CLKCTRL 0x0000000B 0x00070000
    R CM_PER_CM_PER_TIMER5_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_TIMER6_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_MMC1_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_MMC2_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_TPTC1_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_TPTC2_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_SPINLOCK_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_MAILBOX0_CLKCTRL 0x0000000B 0x00030000
    R CM_PER_CM_PER_L4HS_CLKSTCTRL 0x0000000B 0x0000007A
    R CM_PER_CM_PER_L4HS_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_OCPWP_L3_CLKSTCTRL 0x0000000B 0x00000012
    R CM_PER_CM_PER_OCPWP_CLKCTRL 0x0000000B 0x00040002
    R CM_PER_CM_PER_PRU_ICSS_CLKSTCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_CPSW_CLKSTCTRL 0x0000000B 0x00000012
    R CM_PER_CM_PER_LCDC_CLKSTCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_CLKDIV32K_CLKCTRL 0x0000000B 0x00000002
    R CM_PER_CM_PER_CLK_24MHZ_CLKSTCTRL 0x0000000B 0x00000012
    R CM_WKUP_CM_WKUP_CLKSTCTRL 0x0000000B 0x00001E16
    R CM_WKUP_CM_WKUP_CONTROL_CLKCTRL 0x0000000B 0x00000002
    R CM_WKUP_CM_WKUP_GPIO0_CLKCTRL 0x0000000B 0x00000002
    R CM_WKUP_CM_WKUP_L4WKUP_CLKCTRL 0x0000000B 0x00000002
    R CM_WKUP_CM_WKUP_TIMER0_CLKCTRL 0x0000000B 0x00000002
    R CM_WKUP_CM_WKUP_DEBUGSS_CLKCTRL 0x0000000B 0x52580002
    R CM_WKUP_CM_L3_AON_CLKSTCTRL 0x0000000B 0x0000001E
    R CM_WKUP_CM_AUTOIDLE_DPLL_MPU 0x0000000B 0x00000000
    R CM_WKUP_CM_IDLEST_DPLL_MPU 0x0000000B 0x00000001
    R CM_WKUP_CM_SSC_DELTAMSTEP_DPLL_MPU 0x0000000B 0x00000000
    R CM_WKUP_CM_SSC_MODFREQDIV_DPLL_MPU 0x0000000B 0x00000000
    R CM_WKUP_CM_CLKSEL_DPLL_MPU 0x0000000B 0x00001900
    R CM_WKUP_CM_AUTOIDLE_DPLL_DDR 0x0000000B 0x00000000
    R CM_WKUP_CM_IDLEST_DPLL_DDR 0x0000000B 0x00000001
    R CM_WKUP_CM_SSC_DELTAMSTEP_DPLL_DDR 0x0000000B 0x00000000
    R CM_WKUP_CM_SSC_MODFREQDIV_DPLL_DDR 0x0000000B 0x00000000
    R CM_WKUP_CM_CLKSEL_DPLL_DDR 0x0000000B 0x00003202
    R CM_WKUP_CM_AUTOIDLE_DPLL_DISP 0x0000000B 0x00000000
    R CM_WKUP_CM_IDLEST_DPLL_DISP 0x0000000B 0x00000001
    R CM_WKUP_CM_SSC_DELTAMSTEP_DPLL_DISP 0x0000000B 0x00000000
    R CM_WKUP_CM_SSC_MODFREQDIV_DPLL_DISP 0x0000000B 0x00000000
    R CM_WKUP_CM_CLKSEL_DPLL_DISP 0x0000000B 0x00000200
    R CM_WKUP_CM_AUTOIDLE_DPLL_CORE 0x0000000B 0x00000000
    R CM_WKUP_CM_IDLEST_DPLL_CORE 0x0000000B 0x00000001
    R CM_WKUP_CM_SSC_DELTAMSTEP_DPLL_CORE 0x0000000B 0x00000000
    R CM_WKUP_CM_SSC_MODFREQDIV_DPLL_CORE 0x0000000B 0x00000000
    R CM_WKUP_CM_CLKSEL_DPLL_CORE 0x0000000B 0x00007D02
    R CM_WKUP_CM_AUTOIDLE_DPLL_PER 0x0000000B 0x00000000
    R CM_WKUP_CM_IDLEST_DPLL_PER 0x0000000B 0x00000001
    R CM_WKUP_CM_SSC_DELTAMSTEP_DPLL_PER 0x0000000B 0x00000000
    R CM_WKUP_CM_SSC_MODFREQDIV_DPLL_PER 0x0000000B 0x00000000
    R CM_WKUP_CM_CLKDCOLDO_DPLL_PER 0x0000000B 0x00000000
    R CM_WKUP_CM_DIV_M4_DPLL_CORE 0x0000000B 0x0000022A
    R CM_WKUP_CM_DIV_M5_DPLL_CORE 0x0000000B 0x00000228
    R CM_WKUP_CM_CLKMODE_DPLL_MPU 0x0000000B 0x00000007
    R CM_WKUP_CM_CLKMODE_DPLL_PER 0x0000000B 0x00000007
    R CM_WKUP_CM_CLKMODE_DPLL_CORE 0x0000000B 0x00000007
    R CM_WKUP_CM_CLKMODE_DPLL_DDR 0x0000000B 0x00000007
    R CM_WKUP_CM_CLKMODE_DPLL_DISP 0x0000000B 0x00000007
    R CM_WKUP_CM_CLKSEL_DPLL_PERIPH 0x0000000B 0x04019009
    R CM_WKUP_CM_DIV_M2_DPLL_DDR 0x0000000B 0x00000201
    R CM_WKUP_CM_DIV_M2_DPLL_DISP 0x0000000B 0x00000301
    R CM_WKUP_CM_DIV_M2_DPLL_MPU 0x0000000B 0x00000201
    R CM_WKUP_CM_DIV_M2_DPLL_PER 0x0000000B 0x00000385
    R CM_WKUP_CM_WKUP_WKUP_M3_CLKCTRL 0x0000000B 0x00040002
    R CM_WKUP_CM_WKUP_UART0_CLKCTRL 0x0000000B 0x00000002
    R CM_WKUP_CM_WKUP_I2C0_CLKCTRL 0x0000000B 0x00000002
    R CM_WKUP_CM_WKUP_ADC_TSC_CLKCTRL 0x0000000B 0x00030000
    R CM_WKUP_CM_WKUP_SMARTREFLEX0_CLKCTRL 0x0000000B 0x00030000
    R CM_WKUP_CM_WKUP_TIMER1_CLKCTRL 0x0000000B 0x00030000
    R CM_WKUP_CM_WKUP_SMARTREFLEX1_CLKCTRL 0x0000000B 0x00030000
    R CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL 0x0000000B 0x00000006
    R CM_WKUP_CM_WKUP_WDT1_CLKCTRL 0x0000000B 0x00000002
    R CM_WKUP_CM_DIV_M6_DPLL_CORE 0x0000000B 0x00000004
    R CM_DPLL_CLKSEL_TIMER7_CLK 0x0000000B 0x00000001
    R CM_DPLL_CLKSEL_TIMER2_CLK 0x0000000B 0x00000002
    R CM_DPLL_CLKSEL_TIMER3_CLK 0x0000000B 0x00000000
    R CM_DPLL_CLKSEL_TIMER4_CLK 0x0000000B 0x00000001
    R CM_DPLL_CM_MAC_CLKSEL 0x0000000B 0x00000004
    R CM_DPLL_CLKSEL_TIMER5_CLK 0x0000000B 0x00000001
    R CM_DPLL_CLKSEL_TIMER6_CLK 0x0000000B 0x00000000
    R CM_DPLL_CM_CPTS_RFT_CLKSEL 0x0000000B 0x00000000
    R CM_DPLL_CLKSEL_TIMER1MS_CLK 0x0000000B 0x00000000
    R CM_DPLL_CLKSEL_GFX_FCLK 0x0000000B 0x00000000
    R CM_DPLL_CLKSEL_PRU_ICSS_OCP_CLK 0x0000000B 0x00000000
    R CM_DPLL_CLKSEL_LCDC_PIXEL_CLK 0x0000000B 0x00000000
    R CM_DPLL_CLKSEL_WDT1_CLK 0x0000000B 0x00000000
    R CM_DPLL_CLKSEL_GPIO0_DBCLK 0x0000000B 0x00000000
    R CM_MPU_CM_MPU_CLKSTCTRL 0x0000000B 0x00000006
    R CM_MPU_CM_MPU_MPU_CLKCTRL 0x0000000B 0x00000002
    R CM_DEVICE_CM_CLKOUT_CTRL 0x0000000B 0x00000000
    R CM_RTC_CM_RTC_RTC_CLKCTRL 0x0000000B 0x00000002
    R CM_RTC_CM_RTC_CLKSTCTRL 0x0000000B 0x00000302
    R CM_GFX_CM_GFX_L3_CLKSTCTRL 0x0000000B 0x00000002
    R CM_GFX_CM_GFX_GFX_CLKCTRL 0x0000000B 0x00070000
    R CM_GFX_CM_GFX_L4LS_GFX_CLKSTCTRL 0x0000000B 0x00000002
    R CM_GFX_CM_GFX_MMUCFG_CLKCTRL 0x0000000B 0x00030000
    R CM_GFX_CM_GFX_MMUDATA_CLKCTRL 0x0000000B 0x00030000
    R CM_CEFUSE_CM_CEFUSE_CLKSTCTRL 0x0000000B 0x00000002
    R CM_CEFUSE_CM_CEFUSE_CEFUSE_CLKCTRL 0x0000000B 0x00030000
    R PRM_IRQ_REVISION_PRM 0x0000000B 0x00000000
    R PRM_IRQ_PRM_IRQSTATUS_MPU 0x0000000B 0x00000500
    R PRM_IRQ_PRM_IRQENABLE_MPU 0x0000000B 0x00000000
    R PRM_IRQ_PRM_IRQSTATUS_M3 0x0000000B 0x00000100
    R PRM_IRQ_PRM_IRQENABLE_M3 0x0000000B 0x00000000
    R PRM_PER_RM_PER_RSTCTRL 0x0000000B 0x00000003
    R PRM_PER_PM_PER_PWRSTST 0x0000000B 0x01E60007
    R PRM_PER_PM_PER_PWRSTCTRL 0x0000000B 0xEE0000EB
    R PRM_WKUP_RM_WKUP_RSTCTRL 0x0000000B 0x00000008
    R PRM_WKUP_PM_WKUP_PWRSTCTRL 0x0000000B 0x00000008
    R PRM_WKUP_PM_WKUP_PWRSTST 0x0000000B 0x00000000
    R PRM_WKUP_RM_WKUP_RSTST 0x0000000B 0x00000000
    R PRM_MPU_PM_MPU_PWRSTCTRL 0x0000000B 0x01FF0007
    R PRM_MPU_PM_MPU_PWRSTST 0x0000000B 0x000003F7
    R PRM_MPU_RM_MPU_RSTST 0x0000000B 0x00000000
    R PRM_DEVICE_PRM_RSTCTRL 0x0000000B 0x00000000
    R PRM_DEVICE_PRM_RSTTIME 0x0000000B 0x00001006
    R PRM_DEVICE_PRM_RSTST 0x0000000B 0x00000221
    R PRM_DEVICE_PRM_SRAM_COUNT 0x0000000B 0x78000017
    R PRM_DEVICE_PRM_LDO_SRAM_CORE_SETUP 0x0000000B 0x00000003
    R PRM_DEVICE_PRM_LDO_SRAM_CORE_CTRL 0x0000000B 0x00000000
    R PRM_DEVICE_PRM_LDO_SRAM_MPU_SETUP 0x0000000B 0x00000003
    R PRM_DEVICE_PRM_LDO_SRAM_MPU_CTRL 0x0000000B 0x00000000
    R PRM_RTC_PM_RTC_PWRSTCTRL 0x0000000B 0x00000004
    R PRM_RTC_PM_RTC_PWRSTST 0x0000000B 0x00000000
    R PRM_GFX_PM_GFX_PWRSTCTRL 0x0000000B 0x00060044
    R PRM_GFX_RM_GFX_RSTCTRL 0x0000000B 0x00000001
    R PRM_GFX_PM_GFX_PWRSTST 0x0000000B 0x00000037
    R PRM_GFX_RM_GFX_RSTST 0x0000000B 0x00000001
    R PRM_CEFUSE_PM_CEFUSE_PWRSTCTRL 0x0000000B 0x00000000
    R PRM_CEFUSE_PM_CEFUSE_PWRSTST 0x0000000B 0x00000007
    R DMTIMER0_TIDR 0x0000000B 0x4FFF1301
    R DMTIMER0_TIOCP_CFG 0x0000000B 0x00000000
    R DMTIMER0_IRQSTATUS_RAW 0x0000000B 0x00000000
    R DMTIMER0_IRQSTATUS 0x0000000B 0x00000000
    R DMTIMER0_IRQENABLE_SET 0x0000000B 0x00000000
    R DMTIMER0_IRQENABLE_CLR 0x0000000B 0x00000000
    R DMTIMER0_IRQWAKEEN 0x0000000B 0x00000000
    R DMTIMER0_TCLR 0x0000000B 0x00000000
    R DMTIMER0_TCRR 0x0000000B 0x00000000
    R DMTIMER0_TLDR 0x0000000B 0x00000000
    R DMTIMER0_TTGR 0x0000000B 0xFFFFFFFF
    R DMTIMER0_TWPS 0x0000000B 0x00000000
    R DMTIMER0_TMAR 0x0000000B 0x00000000
    R DMTIMER0_TCAR1 0x0000000B 0x00000000
    R DMTIMER0_TSICR 0x0000000B 0x00000004
    R DMTIMER0_TCAR2 0x0000000B 0x00000000
    R GPIO0_GPIO_REVISION 0x0000000B 0x50600801
    R GPIO0_GPIO_SYSCONFIG 0x0000000B 0x00000000
    R GPIO0_GPIO_IRQSTATUS_RAW_0 0x0000000B 0x00000000
    R GPIO0_GPIO_IRQSTATUS_RAW_1 0x0000000B 0x00000000
    R GPIO0_GPIO_IRQSTATUS_0 0x0000000B 0x00000000
    R GPIO0_GPIO_IRQSTATUS_1 0x0000000B 0x00000000
    R GPIO0_GPIO_IRQSTATUS_SET_0 0x0000000B 0x00000000
    R GPIO0_GPIO_IRQSTATUS_SET_1 0x0000000B 0x00000000
    R GPIO0_GPIO_IRQSTATUS_CLR_0 0x0000000B 0x00000000
    R GPIO0_GPIO_IRQSTATUS_CLR_1 0x0000000B 0x00000000
    R GPIO0_GPIO_IRQWAKEN_0 0x0000000B 0x00000000
    R GPIO0_GPIO_IRQWAKEN_1 0x0000000B 0x00000000
    R GPIO0_GPIO_SYSSTATUS 0x0000000B 0x00000000
    R GPIO0_GPIO_CTRL 0x0000000B 0x00000002
    R GPIO0_GPIO_OE 0x0000000B 0xFFFFFFFF
    R GPIO0_GPIO_DATAIN 0x0000000B 0xC000F47C
    R GPIO0_GPIO_DATAOUT 0x0000000B 0x00000000
    R GPIO0_GPIO_LEVELDETECT0 0x0000000B 0x00000000
    R GPIO0_GPIO_LEVELDETECT1 0x0000000B 0x00000000
    R GPIO0_GPIO_RISINGDETECT 0x0000000B 0x00000000
    R GPIO0_GPIO_FALLINGDETECT 0x0000000B 0x00000000
    R GPIO0_GPIO_DEBOUNCENABLE 0x0000000B 0x00000000
    R GPIO0_GPIO_DEBOUNCINGTIME 0x0000000B 0x00000000
    R GPIO0_GPIO_CLEARDATAOUT 0x0000000B 0x00000000
    R GPIO0_GPIO_SETDATAOUT 0x0000000B 0x00000000
    R UART0_DLL 0x0000000F 0x0000
    R UART0_RHR 0x0000000F 0x0000
    R UART0_THR 0x0000000F 0x0000
    R UART0_DLH 0x0000000F 0x0000
    R UART0_IER_CIR 0x0000000F 0x0000
    R UART0_IER_UART 0x0000000F 0x0000
    R UART0_IER_IRDA 0x0000000F 0x0000
    R UART0_IIR_CIR 0x0000000F 0x00C1
    R UART0_IIR_IRDA 0x0000000F 0x00C1
    R UART0_FCR 0x0000000F 0x00C1
    R UART0_IIR_UART 0x0000000F 0x00C1
    R UART0_EFR 0x0000000F 0x00C1
    R UART0_LCR 0x0000000F 0x0003
    R UART0_XON1_ADDR1 0x0000000F 0x0000
    R UART0_MCR 0x0000000F 0x0000
    R UART0_LSR_UART 0x0000000F 0x0060
    R UART0_LSR_CIR 0x0000000F 0x0060
    R UART0_LSR_IRDA 0x0000000F 0x0060
    R UART0_XON2_ADDR2 0x0000000F 0x0060
    R UART0_XOFF1 0x0000000F 0x0033
    R UART0_MSR 0x0000000F 0x0030
    R UART0_TCR 0x0000000F 0x0030
    R UART0_TLR 0x0000000F 0x0000
    R UART0_XOFF2 0x0000000F 0x0000
    R UART0_SPR 0x0000000F 0x0000
    R UART0_MDR1 0x0000000F 0x0000
    R UART0_MDR2 0x0000000F 0x0000
    R UART0_SFLSR 0x0000000F 0x0000
    R UART0_TXFLL 0x0000000F 0x0000
    R UART0_TXFLH 0x0000000F 0x0000
    R UART0_RESUME 0x0000000F 0x0000
    R UART0_SFREGL 0x0000000F 0x0000
    R UART0_RXFLL 0x0000000F 0x0000
    R UART0_RXFLH 0x0000000F 0x0001
    R UART0_SFREGH 0x0000000F 0x0001
    R UART0_UASR 0x0000000F 0x0040
    R UART0_BLR 0x0000000F 0x0040
    R UART0_ACREG 0x0000000F 0x0000
    R UART0_SCR 0x0000000F 0x0000
    R UART0_SSR 0x0000000F 0x0004
    R UART0_EBLR 0x0000000F 0x0000
    R UART0_MVR 0x0000000F 0x2603
    R UART0_SYSC 0x0000000F 0x0000
    R UART0_SYSS 0x0000000F 0x0001
    R UART0_WER 0x0000000F 0x00FF
    R UART0_CFPS 0x0000000F 0x0069
    R UART0_RXFIFO_LVL 0x0000000F 0x0000
    R UART0_TXFIFO_LVL 0x0000000F 0x0000
    R UART0_IER2 0x0000000F 0x0000
    R UART0_ISR2 0x0000000F 0x0003
    R UART0_FREQ_SEL 0x0000000F 0x001A
    R UART0_MDR3 0x0000000F 0x0000
    R UART0_TX_DMA_THRESHOLD 0x0000000F 0x0000
    R I2C0_I2C_REVNB_LO 0x0000000B 0x0000000B
    R I2C0_I2C_REVNB_HI 0x0000000B 0x00005040
    R I2C0_I2C_SYSC 0x0000000B 0x00000001
    R I2C0_I2C_IRQSTATUS_RAW 0x0000000B 0x00000000
    R I2C0_I2C_IRQSTATUS 0x0000000B 0x00000000
    R I2C0_I2C_IRQENABLE_SET 0x0000000B 0x00000000
    R I2C0_I2C_IRQENABLE_CLR 0x0000000B 0x00000000
    R I2C0_I2C_WE 0x0000000B 0x00000000
    R I2C0_I2C_DMARXENABLE_SET 0x0000000B 0x00000000
    R I2C0_I2C_DMATXENABLE_SET 0x0000000B 0x00000000
    R I2C0_I2C_DMARXENABLE_CLR 0x0000000B 0x00000000
    R I2C0_I2C_DMATXENABLE_CLR 0x0000000B 0x00000000
    R I2C0_I2C_DMARXWAKE_EN 0x0000000B 0x00000000
    R I2C0_I2C_DMATXWAKE_EN 0x0000000B 0x00000000
    R I2C0_I2C_SYSS 0x0000000B 0x00000000
    R I2C0_I2C_BUF 0x0000000B 0x00000000
    R I2C0_I2C_CNT 0x0000000B 0x00000000
    R I2C0_I2C_DATA 0x0000000B 0x0000007F
    R I2C0_I2C_CON 0x0000000B 0x00000000
    R I2C0_I2C_OA 0x0000000B 0x00000000
    R I2C0_I2C_SA 0x0000000B 0x000003FF
    R I2C0_I2C_PSC 0x0000000B 0x00000000
    R I2C0_I2C_SCLL 0x0000000B 0x00000000
    R I2C0_I2C_SCLH 0x0000000B 0x00000000
    R I2C0_I2C_SYSTEST 0x0000000B 0x000001E0
    R I2C0_I2C_BUFSTAT 0x0000000B 0x00008000
    R I2C0_I2C_OA1 0x0000000B 0x00000000
    R I2C0_I2C_OA2 0x0000000B 0x00000000
    R I2C0_I2C_OA3 0x0000000B 0x00000000
    R I2C0_I2C_ACTOA 0x0000000B 0x00000000
    R I2C0_I2C_SBLOCK 0x0000000B 0x00000000
    R Control_Module_control_revision 0x0000000B 0x4E8B0100
    R Control_Module_control_hwinfo 0x0000000B 0x00000000
    R Control_Module_control_sysconfig 0x0000000B 0x0000002A
    R Control_Module_control_status 0x0000000B 0x0040033C
    R Control_Module_control_emif_sdram_config 0x0000000B 0x61405332
    R Control_Module_cortex_vbbldo_ctrl 0x0000000B 0x00000000
    R Control_Module_core_sldo_ctrl 0x0000000B 0x001F0000
    R Control_Module_mpu_sldo_ctrl 0x0000000B 0x001F0000
    R Control_Module_clk32kdivratio_ctrl 0x0000000B 0x00000000
    R Control_Module_bandgap_ctrl 0x0000000B 0x0000361E
    R Control_Module_bandgap_trim 0x0000000B 0x7EA74500
    R Control_Module_pll_clkinpulow_ctrl 0x0000000B 0x00000000
    R Control_Module_mosc_ctrl 0x0000000B 0x00000000
    R Control_Module_deepsleep_ctrl 0x0000000B 0x00006A75
    R Control_Module_dpll_pwr_sw_status 0x0000000B 0x03030300
    R Control_Module_device_id 0x0000000B 0x2B94402E
    R Control_Module_dev_feature 0x0000000B 0x20FD0383
    R Control_Module_init_priority_0 0x0000000B 0x00000000
    R Control_Module_init_priority_1 0x0000000B 0x00000000
    R Control_Module_mmu_cfg 0x0000000B 0x00000000
    R Control_Module_tptc_cfg 0x0000000B 0x0000003F
    R Control_Module_usb_ctrl0 0x0000000B 0x3C006007
    R Control_Module_usb_sts0 0x0000000B 0x00000000
    R Control_Module_usb_ctrl1 0x0000000B 0x3C006007
    R Control_Module_usb_sts1 0x0000000B 0x00000000
    R Control_Module_mac_id0_lo 0x0000000B 0x00007055
    R Control_Module_mac_id0_hi 0x0000000B 0x10CCD5B0
    R Control_Module_mac_id1_lo 0x0000000B 0x00007255
    R Control_Module_mac_id1_hi 0x0000000B 0x10CCD5B0
    R Control_Module_dcan_raminit 0x0000000B 0x00000000
    R Control_Module_usb_wkup_ctrl 0x0000000B 0x00000000
    R Control_Module_gmii_sel 0x0000000B 0x00000000
    R Control_Module_pwmss_ctrl 0x0000000B 0x00000000
    R Control_Module_mreqprio_0 0x0000000B 0x44444444
    R Control_Module_mreqprio_1 0x0000000B 0x00000004
    R Control_Module_hw_event_sel_grp1 0x0000000B 0x00000000
    R Control_Module_hw_event_sel_grp2 0x0000000B 0x00000000
    R Control_Module_hw_event_sel_grp3 0x0000000B 0x00000000
    R Control_Module_hw_event_sel_grp4 0x0000000B 0x00000000
    R Control_Module_smrt_ctrl 0x0000000B 0x00000003
    R Control_Module_mpuss_hw_debug_sel 0x0000000B 0x00000200
    R Control_Module_mpuss_hw_dbg_info 0x0000000B 0xFD987FFE
    R Control_Module_vdd_mpu_opp_050 0x0000000B 0x0099BDAB
    R Control_Module_vdd_mpu_opp_100 0x0000000B 0x00999483
    R Control_Module_vdd_mpu_opp_120 0x0000000B 0x00AAEAD0
    R Control_Module_vdd_mpu_opp_turbo 0x0000000B 0x00AAC8B2
    R Control_Module_vdd_core_opp_050 0x0000000B 0x0099BFB3
    R Control_Module_vdd_core_opp_100 0x0000000B 0x00998B80
    R Control_Module_bb_scale 0x0000000B 0x00000000
    R Control_Module_usb_vid_pid 0x0000000B 0x00000000
    R Control_Module_efuse_sma 0x0000000B 0x00013C2F
    R Control_Module_conf_gpmc_ad_0 0x0000000B 0x00000031
    R Control_Module_conf_gpmc_ad_1 0x0000000B 0x00000031
    R Control_Module_conf_gpmc_ad_2 0x0000000B 0x00000031
    R Control_Module_conf_gpmc_ad_3 0x0000000B 0x00000031
    R Control_Module_conf_gpmc_ad_4 0x0000000B 0x00000031
    R Control_Module_conf_gpmc_ad_5 0x0000000B 0x00000031
    R Control_Module_conf_gpmc_ad_6 0x0000000B 0x00000031
    R Control_Module_conf_gpmc_ad_7 0x0000000B 0x00000031
    R Control_Module_conf_gpmc_ad_8 0x0000000B 0x00000027
    R Control_Module_conf_gpmc_ad_9 0x0000000B 0x00000027
    R Control_Module_conf_gpmc_ad_10 0x0000000B 0x00000027
    R Control_Module_conf_gpmc_ad_11 0x0000000B 0x00000027
    R Control_Module_conf_gpmc_ad_12 0x0000000B 0x00000027
    R Control_Module_conf_gpmc_ad_13 0x0000000B 0x00000027
    R Control_Module_conf_gpmc_ad_14 0x0000000B 0x00000027
    R Control_Module_conf_gpmc_ad_15 0x0000000B 0x00000027
    R Control_Module_conf_gpmc_a 0x0000000B 0x00000027
    R Control_Module_conf_gpmc_wait0 0x0000000B 0x00000037
    R Control_Module_conf_gpmc_wpn 0x0000000B 0x00000037
    R Control_Module_conf_gpmc_ben1 0x0000000B 0x00000037
    R Control_Module_conf_gpmc_csn_0 0x0000000B 0x00000037
    R Control_Module_conf_gpmc_csn_1 0x0000000B 0x00000032
    R Control_Module_conf_gpmc_csn_2 0x0000000B 0x00000032
    R Control_Module_conf_gpmc_csn_3 0x0000000B 0x00000037
    R Control_Module_conf_gpmc_clk 0x0000000B 0x00000027
    R Control_Module_conf_gpmc_advn_ale 0x0000000B 0x00000037
    R Control_Module_conf_gpmc_oen_ren 0x0000000B 0x00000037
    R Control_Module_conf_gpmc_wen 0x0000000B 0x00000037
    R Control_Module_conf_gpmc_ben0_cle 0x0000000B 0x00000037
    R Control_Module_conf_lcd_data_0 0x0000000B 0x0000002F
    R Control_Module_conf_lcd_data_1 0x0000000B 0x0000002F
    R Control_Module_conf_lcd_data_2 0x0000000B 0x0000002F
    R Control_Module_conf_lcd_data_3 0x0000000B 0x0000002F
    R Control_Module_conf_lcd_data_4 0x0000000B 0x0000002F
    R Control_Module_conf_lcd_data_5 0x0000000B 0x0000002F
    R Control_Module_conf_lcd_data_6 0x0000000B 0x0000002F
    R Control_Module_conf_lcd_data_7 0x0000000B 0x0000002F
    R Control_Module_conf_lcd_data_8 0x0000000B 0x0000002F
    R Control_Module_conf_lcd_data_9 0x0000000B 0x0000002F
    R Control_Module_conf_lcd_data_10 0x0000000B 0x0000002F
    R Control_Module_conf_lcd_data_11 0x0000000B 0x0000002F
    R Control_Module_conf_lcd_data_12 0x0000000B 0x0000002F
    R Control_Module_conf_lcd_data_13 0x0000000B 0x0000002F
    R Control_Module_conf_lcd_data_14 0x0000000B 0x0000002F
    R Control_Module_conf_lcd_data_15 0x0000000B 0x0000002F
    R Control_Module_conf_lcd_vsync 0x0000000B 0x00000027
    R Control_Module_conf_lcd_hsync 0x0000000B 0x00000027
    R Control_Module_conf_lcd_pclk 0x0000000B 0x00000027
    R Control_Module_conf_lcd_ac_bias_en 0x0000000B 0x00000027
    R Control_Module_conf_mmc0_dat_0 0x0000000B 0x00000030
    R Control_Module_conf_mmc0_dat_1 0x0000000B 0x00000030
    R Control_Module_conf_mmc0_dat_2 0x0000000B 0x00000030
    R Control_Module_conf_mmc0_dat_3 0x0000000B 0x00000030
    R Control_Module_conf_mmc0_clk 0x0000000B 0x00000030
    R Control_Module_conf_mmc0_cmd 0x0000000B 0x00000030
    R Control_Module_conf_mii1_col 0x0000000B 0x00000028
    R Control_Module_conf_mii1_crs 0x0000000B 0x00000028
    R Control_Module_conf_mii1_rx_er 0x0000000B 0x00000028
    R Control_Module_conf_mii1_tx_en 0x0000000B 0x00000008
    R Control_Module_conf_mii1_rx_dv 0x0000000B 0x00000028
    R Control_Module_conf_mii1_txd_0 0x0000000B 0x00000008
    R Control_Module_conf_mii1_txd_1 0x0000000B 0x00000008
    R Control_Module_conf_mii1_txd_2 0x0000000B 0x00000008
    R Control_Module_conf_mii1_txd_3 0x0000000B 0x00000008
    R Control_Module_conf_mii1_tx_clk 0x0000000B 0x00000028
    R Control_Module_conf_mii1_rx_clk 0x0000000B 0x00000028
    R Control_Module_conf_mii1_rxd3 0x0000000B 0x00000028
    R Control_Module_conf_mii1_rxd2 0x0000000B 0x00000028
    R Control_Module_conf_mii1_rxd1 0x0000000B 0x00000028
    R Control_Module_conf_mii1_rxd0 0x0000000B 0x00000028
    R Control_Module_conf_rmii1_ref_clk 0x0000000B 0x00000027
    R Control_Module_conf_mdio 0x0000000B 0x00000030
    R Control_Module_conf_mdc 0x0000000B 0x00000010
    R Control_Module_conf_spi0_sclk 0x0000000B 0x00000037
    R Control_Module_conf_spi0_d0 0x0000000B 0x00000037
    R Control_Module_conf_spi0_d1 0x0000000B 0x00000037
    R Control_Module_conf_spi0_cs0 0x0000000B 0x00000037
    R Control_Module_conf_spi0_cs1 0x0000000B 0x00000037
    R Control_Module_conf_ecap0_in_pwm0_out 0x0000000B 0x00000027
    R Control_Module_conf_uart0_ctsn 0x0000000B 0x00000037
    R Control_Module_conf_uart0_rtsn 0x0000000B 0x00000037
    R Control_Module_conf_uart0_rxd 0x0000000B 0x00000030
    R Control_Module_conf_uart0_txd 0x0000000B 0x00000010
    R Control_Module_conf_uart1_ctsn 0x0000000B 0x00000037
    R Control_Module_conf_uart1_rtsn 0x0000000B 0x00000037
    R Control_Module_conf_uart1_rxd 0x0000000B 0x00000037
    R Control_Module_conf_uart1_txd 0x0000000B 0x00000037
    R Control_Module_conf_i2c0_sda 0x0000000B 0x00000028
    R Control_Module_conf_i2c0_scl 0x0000000B 0x00000028
    R Control_Module_conf_mcasp0_aclkx 0x0000000B 0x0000002B
    R Control_Module_conf_mcasp0_fsx 0x0000000B 0x0000002B
    R Control_Module_conf_mcasp0_axr0 0x0000000B 0x00000033
    R Control_Module_conf_mcasp0_ahclkr 0x0000000B 0x00000033
    R Control_Module_conf_mcasp0_aclkr 0x0000000B 0x00000027
    R Control_Module_conf_mcasp0_fsr 0x0000000B 0x0000000F
    R Control_Module_conf_mcasp0_axr1 0x0000000B 0x00000027
    R Control_Module_conf_mcasp0_ahclkx 0x0000000B 0x00000027
    R Control_Module_conf_xdma_event_intr0 0x0000000B 0x00000023
    R Control_Module_conf_xdma_event_intr1 0x0000000B 0x00000027
    R Control_Module_conf_warmrstn 0x0000000B 0x00000030
    R Control_Module_conf_nnmi 0x0000000B 0x00000030
    R Control_Module_conf_tms 0x0000000B 0x00000030
    R Control_Module_conf_tdi 0x0000000B 0x00000030
    R Control_Module_conf_tdo 0x0000000B 0x00000030
    R Control_Module_conf_tck 0x0000000B 0x00000030
    R Control_Module_conf_trstn 0x0000000B 0x00000020
    R Control_Module_conf_emu0 0x0000000B 0x00000030
    R Control_Module_conf_emu1 0x0000000B 0x00000030
    R Control_Module_conf_rtc_pwronrstn 0x0000000B 0x00000030
    R Control_Module_conf_pmic_power_en 0x0000000B 0x00000028
    R Control_Module_conf_ext_wakeup 0x0000000B 0x00000028
    R Control_Module_conf_rtc_kaldo_enn 0x0000000B 0x00000020
    R Control_Module_conf_usb0_drvvbus 0x0000000B 0x00000020
    R Control_Module_conf_usb1_drvvbus 0x0000000B 0x00000020
    R Control_Module_cqdetect_status 0x0000000B 0x00003F3F
    R Control_Module_ddr_io_ctrl 0x0000000B 0x00000000
    R Control_Module_vtp_ctrl 0x0000000B 0x00000067
    R Control_Module_vref_ctrl 0x0000000B 0x00000000
    R Control_Module_tpcc_evt_mux_0_3 0x0000000B 0x00000000
    R Control_Module_tpcc_evt_mux_4_7 0x0000000B 0x00000000
    R Control_Module_tpcc_evt_mux_8_11 0x0000000B 0x00000000
    R Control_Module_tpcc_evt_mux_12_15 0x0000000B 0x00000000
    R Control_Module_tpcc_evt_mux_16_19 0x0000000B 0x00000000
    R Control_Module_tpcc_evt_mux_20_23 0x0000000B 0x00000000
    R Control_Module_tpcc_evt_mux_24_27 0x0000000B 0x00000000
    R Control_Module_tpcc_evt_mux_28_31 0x0000000B 0x00000000
    R Control_Module_tpcc_evt_mux_32_35 0x0000000B 0x00000000
    R Control_Module_tpcc_evt_mux_36_39 0x0000000B 0x00000000
    R Control_Module_tpcc_evt_mux_40_43 0x0000000B 0x00000000
    R Control_Module_tpcc_evt_mux_44_47 0x0000000B 0x00000000
    R Control_Module_tpcc_evt_mux_48_51 0x0000000B 0x00000000
    R Control_Module_tpcc_evt_mux_52_55 0x0000000B 0x00000000
    R Control_Module_tpcc_evt_mux_56_59 0x0000000B 0x00000000
    R Control_Module_tpcc_evt_mux_60_63 0x0000000B 0x00000000
    R Control_Module_timer_evt_capt 0x0000000B 0x00000000
    R Control_Module_ecap_evt_capt 0x0000000B 0x00000000
    R Control_Module_adc_evt_capt 0x0000000B 0x00000000
    R Control_Module_reset_iso 0x0000000B 0x00000000
    R Control_Module_dpll_pwr_sw_ctrl 0x0000000B 0x03030303
    R Control_Module_ddr_cke_ctrl 0x0000000B 0x00000001
    R Control_Module_sma2 0x0000000B 0x00000000
    R Control_Module_m3_txev_eoi 0x0000000B 0x00000000
    R Control_Module_ipc_msg_reg0 0x0000000B 0x00000000
    R Control_Module_ipc_msg_reg1 0x0000000B 0x00000000
    R Control_Module_ipc_msg_reg2 0x0000000B 0x00000000
    R Control_Module_ipc_msg_reg3 0x0000000B 0x00000000
    R Control_Module_ipc_msg_reg4 0x0000000B 0x00000000
    R Control_Module_ipc_msg_reg5 0x0000000B 0x00000000
    R Control_Module_ipc_msg_reg6 0x0000000B 0x00000000
    R Control_Module_ipc_msg_reg7 0x0000000B 0x00000000
    R Control_Module_ddr_cmd0_ioctrl 0x0000000B 0x0000018B
    R Control_Module_ddr_cmd1_ioctrl 0x0000000B 0x0000018B
    R Control_Module_ddr_cmd2_ioctrl 0x0000000B 0x0000018B
    R Control_Module_ddr_data0_ioctrl 0x0000000B 0x0000018B
    R Control_Module_ddr_data1_ioctrl 0x0000000B 0x0000018B
    R DDR2_3_PHY_CMD0_REG_PHY_CTRL_SLAVE_RATIO_0 0x0000000B 0x00000000
    R DDR2_3_PHY_CMD0_REG_PHY_DLL_LOCK_DIFF_0 0x0000000B 0x00000000
    R DDR2_3_PHY_CMD0_REG_PHY_INVERT_CLKOUT_0 0x0000000B 0x00000000
    R DDR2_3_PHY_CMD1_REG_PHY_CTRL_SLAVE_RATIO_0 0x0000000B 0x00000000
    R DDR2_3_PHY_CMD1_REG_PHY_DLL_LOCK_DIFF_0 0x0000000B 0x00000000
    R DDR2_3_PHY_CMD1_REG_PHY_INVERT_CLKOUT_0 0x0000000B 0x00000000
    R DDR2_3_PHY_CMD2_REG_PHY_CTRL_SLAVE_RATIO_0 0x0000000B 0x00000000
    R DDR2_3_PHY_CMD2_REG_PHY_DLL_LOCK_DIFF_0 0x0000000B 0x00000000
    R DDR2_3_PHY_CMD2_REG_PHY_INVERT_CLKOUT_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA0_REG_PHY_WRLVL_INIT_RATIO_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA0_REG_PHY_WRLVL_INIT_MODE_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA0_REG_PHY_GATELVL_INIT_RATIO_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA0_REG_PHY_GATELVL_INIT_MODE_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA0_REG_PHY_DQ_OFFSET_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA0_REG_PHY_USE_RANK0_DELAYS 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA0_REG_PHY_DLL_LOCK_DIFF_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA1_REG_PHY_WRLVL_INIT_RATIO_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA1_REG_PHY_WRLVL_INIT_MODE_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA1_REG_PHY_GATELVL_INIT_RATIO_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA1_REG_PHY_GATELVL_INIT_MODE_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA1_REG_PHY_DQ_OFFSET_1 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA1_REG_PHY_USE_RANK0_DELAYS 0x0000000B 0x00000000
    R DDR2_3_PHY_DATA1_REG_PHY_DLL_LOCK_DIFF_0 0x0000000B 0x00000000
    R WDT1_WDT_WIDR 0x0000000B 0x502A0501
    R WDT1_WDT_WDSC 0x0000000B 0x00000010
    R WDT1_WDT_WDST 0x0000000B 0x00000001
    R WDT1_WDT_WISR 0x0000000B 0x00000000
    R WDT1_WDT_WIER 0x0000000B 0x00000000
    R WDT1_WDT_WCLR 0x0000000B 0x00000020
    R WDT1_WDT_WCRR 0x0000000B 0xFF6A0001
    R WDT1_WDT_WLDR 0x0000000B 0xFF6A0001
    R WDT1_WDT_WTGR 0x0000000B 0xFF6A0001
    R WDT1_WDT_WWPS 0x0000000B 0x00000000
    R WDT1_WDT_WDLY 0x0000000B 0x00000000
    R WDT1_WDT_WSPR 0x0000000B 0x00005555
    R WDT1_WDT_WIRQSTATRAW 0x0000000B 0x00000000
    R WDT1_WDT_WIRQSTAT 0x0000000B 0x00000000
    R WDT1_WDT_WIRQENSET 0x0000000B 0x00000000
    R WDT1_WDT_WIRQENCLR 0x0000000B 0x00000000
    R RTCSS_SECONDS_REG 0x0000000B 0x00000042
    R RTCSS_MINUTES_REG 0x0000000B 0x00000021
    R RTCSS_HOURS_REG 0x0000000B 0x00000022
    R RTCSS_DAYS_REG 0x0000000B 0x00000012
    R RTCSS_MONTHS_REG 0x0000000B 0x00000011
    R RTCSS_YEARS_REG 0x0000000B 0x00000015
    R RTCSS_WEEKS_REG 0x0000000B 0x00000000
    R RTCSS_ALARM_SECONDS_REG 0x0000000B 0x00000009
    R RTCSS_ALARM_MINUTES_REG 0x0000000B 0x00000000
    R RTCSS_ALARM_HOURS_REG 0x0000000B 0x00000000
    R RTCSS_ALARM_DAYS_REG 0x0000000B 0x00000001
    R RTCSS_ALARM_MONTHS_REG 0x0000000B 0x00000001
    R RTCSS_ALARM_YEARS_REG 0x0000000B 0x00000000
    R RTCSS_RTC_CTRL_REG 0x0000000B 0x00000001
    R RTCSS_RTC_STATUS_REG 0x0000000B 0x00000002
    R RTCSS_RTC_INTERRUPTS_REG 0x0000000B 0x00000000
    R RTCSS_RTC_COMP_LSB_REG 0x0000000B 0x00000000
    R RTCSS_RTC_COMP_MSB_REG 0x0000000B 0x00000000
    R RTCSS_RTC_OSC_REG 0x0000000B 0x00000048
    R RTCSS_RTC_SCRATCH0_REG 0x0000000B 0x00000000
    R RTCSS_RTC_SCRATCH1_REG 0x0000000B 0x00000000
    R RTCSS_RTC_SCRATCH2_REG 0x0000000B 0x010001B0
    R RTCSS_KICK0R 0x0000000B 0x010001B0
    R RTCSS_KICK1R 0x0000000B 0x010001B0
    R RTCSS_RTC_REVISION 0x0000000B 0x4EB01106
    R RTCSS_RTC_SYSCONFIG 0x0000000B 0x00000003
    R RTCSS_RTC_IRQWAKEEN 0x0000000B 0x00000000
    R RTCSS_ALARM2_SECONDS_REG 0x0000000B 0x00000000
    R RTCSS_ALARM2_MINUTES_REG 0x0000000B 0x00000000
    R RTCSS_ALARM2_HOURS_REG 0x0000000B 0x00000000
    R RTCSS_ALARM2_DAYS_REG 0x0000000B 0x00000001
    R RTCSS_ALARM2_MONTHS_REG 0x0000000B 0x00000001
    R RTCSS_ALARM2_YEARS_REG 0x0000000B 0x00000000
    R RTCSS_RTC_PMIC 0x0000000B 0x00000000
    R RTCSS_RTC_DEBOUNCE 0x0000000B 0x00000000
    R DMTIMER2_TIDR 0x0000000B 0x4FFF1301
    R DMTIMER2_TIOCP_CFG 0x0000000B 0x00000000
    R DMTIMER2_IRQSTATUS_RAW 0x0000000B 0x00000002
    R DMTIMER2_IRQSTATUS 0x0000000B 0x00000002
    R DMTIMER2_IRQENABLE_SET 0x0000000B 0x00000002
    R DMTIMER2_IRQENABLE_CLR 0x0000000B 0x00000002
    R DMTIMER2_IRQWAKEEN 0x0000000B 0x00000000
    R DMTIMER2_TCLR 0x0000000B 0x00000003
    R DMTIMER2_TCRR 0x0000000B 0xFFFFFFF7
    R DMTIMER2_TLDR 0x0000000B 0xFFFFFFDF
    R DMTIMER2_TTGR 0x0000000B 0xFFFFFFFF
    R DMTIMER2_TWPS 0x0000000B 0x00000000
    R DMTIMER2_TMAR 0x0000000B 0x00000000
    R DMTIMER2_TCAR1 0x0000000B 0x00000000
    R DMTIMER2_TSICR 0x0000000B 0x00000000
    R DMTIMER2_TCAR2 0x0000000B 0x00000000
    R GPIO1_GPIO_REVISION 0x0000000B 0x50600801
    R GPIO1_GPIO_SYSCONFIG 0x0000000B 0x00000000
    R GPIO1_GPIO_IRQSTATUS_RAW_0 0x0000000B 0x10000000
    R GPIO1_GPIO_IRQSTATUS_RAW_1 0x0000000B 0x10000000
    R GPIO1_GPIO_IRQSTATUS_0 0x0000000B 0x10000000
    R GPIO1_GPIO_IRQSTATUS_1 0x0000000B 0x00000000
    R GPIO1_GPIO_IRQSTATUS_SET_0 0x0000000B 0x10000000
    R GPIO1_GPIO_IRQSTATUS_SET_1 0x0000000B 0x00000000
    R GPIO1_GPIO_IRQSTATUS_CLR_0 0x0000000B 0x10000000
    R GPIO1_GPIO_IRQSTATUS_CLR_1 0x0000000B 0x00000000
    R GPIO1_GPIO_IRQWAKEN_0 0x0000000B 0x00000000
    R GPIO1_GPIO_IRQWAKEN_1 0x0000000B 0x00000000
    R GPIO1_GPIO_SYSSTATUS 0x0000000B 0x00000000
    R GPIO1_GPIO_CTRL 0x0000000B 0x00000002
    R GPIO1_GPIO_OE 0x0000000B 0xFFFFFFFF
    R GPIO1_GPIO_DATAIN 0x0000000B 0x26010300
    R GPIO1_GPIO_DATAOUT 0x0000000B 0x00000000
    R GPIO1_GPIO_LEVELDETECT0 0x0000000B 0x00000000
    R GPIO1_GPIO_LEVELDETECT1 0x0000000B 0x00000000
    R GPIO1_GPIO_RISINGDETECT 0x0000000B 0x10000000
    R GPIO1_GPIO_FALLINGDETECT 0x0000000B 0x00000000
    R GPIO1_GPIO_DEBOUNCENABLE 0x0000000B 0x00000000
    R GPIO1_GPIO_DEBOUNCINGTIME 0x0000000B 0x00000000
    R GPIO1_GPIO_CLEARDATAOUT 0x0000000B 0x00000000
    R GPIO1_GPIO_SETDATAOUT 0x0000000B 0x00000000
    R MMCHS0_SD_SYSCONFIG 0x0000000B 0x00002015
    R MMCHS0_SD_SYSSTATUS 0x0000000B 0x00000001
    R MMCHS0_SD_CSRE 0x0000000B 0x00000000
    R MMCHS0_SD_SYSTEST 0x0000000B 0x00000000
    R MMCHS0_SD_CON 0x0000000B 0x00000600
    R MMCHS0_SD_PWCNT 0x0000000B 0x00000000
    R MMCHS0_SD_SDMASA 0x0000000B 0x00000000
    R MMCHS0_SD_BLK 0x0000000B 0x00000000
    R MMCHS0_SD_ARG 0x0000000B 0x00000000
    R MMCHS0_SD_CMD 0x0000000B 0x00000000
    R MMCHS0_SD_RSP10 0x0000000B 0x00000000
    R MMCHS0_SD_RSP32 0x0000000B 0x00000000
    R MMCHS0_SD_RSP54 0x0000000B 0x00000000
    R MMCHS0_SD_RSP76 0x0000000B 0x00000000
    R MMCHS0_SD_DATA 0x0000000B 0x00000000
    R MMCHS0_SD_PSTATE 0x0000000B 0x01F70000
    R MMCHS0_SD_HCTL 0x0000000B 0x00000000
    R MMCHS0_SD_SYSCTL 0x0000000B 0x00000000
    R MMCHS0_SD_STAT 0x0000000B 0x00000040
    R MMCHS0_SD_IE 0x0000000B 0x00000000
    R MMCHS0_SD_ISE 0x0000000B 0x00000000
    R MMCHS0_SD_AC12 0x0000000B 0x00000000
    R MMCHS0_SD_CAPA 0x0000000B 0x00E10080
    R MMCHS0_SD_CUR_CAPA 0x0000000B 0x00000000
    R MMCHS0_SD_FE 0x0000000B 0x00000000
    R MMCHS0_SD_ADMAES 0x0000000B 0x00000000
    R MMCHS0_SD_ADMASAL 0x0000000B 0x00000000
    R MMCHS0_SD_ADMASAH 0x0000000B 0x00000000
    R MMCHS0_SD_REV 0x0000000B 0x31010000
    R McSPI1_MCSPI_REVISION 0x0000000B 0x40300A0B
    R McSPI1_MCSPI_SYSCONFIG 0x0000000B 0x00000308
    R McSPI1_MCSPI_SYSSTATUS 0x0000000B 0x00000001
    R McSPI1_MCSPI_IRQSTATUS 0x0000000B 0x00020001
    R McSPI1_MCSPI_IRQENABLE 0x0000000B 0x00000000
    R McSPI1_MCSPI_SYST 0x0000000B 0x00000000
    R McSPI1_MCSPI_MODULCTRL 0x0000000B 0x00000003
    R McSPI1_MCSPI_CH0CONF 0x0000000B 0x380103D4
    R McSPI1_MCSPI_CH0STAT 0x0000000B 0x0000002E
    R McSPI1_MCSPI_CH0CTRL 0x0000000B 0x00000000
    R McSPI1_MCSPI_TX0 0x0000000B 0x00000000
    R McSPI1_MCSPI_RX0 0x0000000B 0x000000B5
    R McSPI1_MCSPI_CH1CONF 0x0000000B 0x00060000
    R McSPI1_MCSPI_CH1STAT 0x0000000B 0x00000000
    R McSPI1_MCSPI_CH1CTRL 0x0000000B 0x00000000
    R McSPI1_MCSPI_TX1 0x0000000B 0x00000000
    R McSPI1_MCSPI_RX1 0x0000000B 0x00000000
    R McSPI1_MCSPI_CH2CONF 0x0000000B 0x00060000
    R McSPI1_MCSPI_CH2STAT 0x0000000B 0x00000000
    R McSPI1_MCSPI_CH2CTRL 0x0000000B 0x00000000
    R McSPI1_MCSPI_TX2 0x0000000B 0x00000000
    R McSPI1_MCSPI_RX2 0x0000000B 0x00000000
    R McSPI1_MCSPI_CH3CONF 0x0000000B 0x00060000
    R McSPI1_MCSPI_CH3STAT 0x0000000B 0x00000000
    R McSPI1_MCSPI_CH3CTRL 0x0000000B 0x00000000
    R McSPI1_MCSPI_TX3 0x0000000B 0x00000000
    R McSPI1_MCSPI_RX3 0x0000000B 0x00000000
    R McSPI1_MCSPI_XFERLEVEL 0x0000000B 0x00000F0F
    R McSPI1_MCSPI_DAFTX 0x0000000B 0x00000000
    R McSPI1_MCSPI_DAFRX 0x0000000B 0x00000000
    R GPIO2_GPIO_REVISION 0x0000000B 0x50600801
    R GPIO2_GPIO_SYSCONFIG 0x0000000B 0x00000000
    R GPIO2_GPIO_IRQSTATUS_RAW_0 0x0000000B 0x00000000
    R GPIO2_GPIO_IRQSTATUS_RAW_1 0x0000000B 0x00000000
    R GPIO2_GPIO_IRQSTATUS_0 0x0000000B 0x00000000
    R GPIO2_GPIO_IRQSTATUS_1 0x0000000B 0x00000000
    R GPIO2_GPIO_IRQSTATUS_SET_0 0x0000000B 0x00000000
    R GPIO2_GPIO_IRQSTATUS_SET_1 0x0000000B 0x00000000
    R GPIO2_GPIO_IRQSTATUS_CLR_0 0x0000000B 0x00000000
    R GPIO2_GPIO_IRQSTATUS_CLR_1 0x0000000B 0x00000000
    R GPIO2_GPIO_IRQWAKEN_0 0x0000000B 0x00000000
    R GPIO2_GPIO_IRQWAKEN_1 0x0000000B 0x00000000
    R GPIO2_GPIO_SYSSTATUS 0x0000000B 0x00000000
    R GPIO2_GPIO_CTRL 0x0000000B 0x00000002
    R GPIO2_GPIO_OE 0x0000000B 0xFFFFFFFF
    R GPIO2_GPIO_DATAIN 0x0000000B 0x00000F3D
    R GPIO2_GPIO_DATAOUT 0x0000000B 0x00000000
    R GPIO2_GPIO_LEVELDETECT0 0x0000000B 0x00000000
    R GPIO2_GPIO_LEVELDETECT1 0x0000000B 0x00000000
    R GPIO2_GPIO_RISINGDETECT 0x0000000B 0x00000000
    R GPIO2_GPIO_FALLINGDETECT 0x0000000B 0x00000000
    R GPIO2_GPIO_DEBOUNCENABLE 0x0000000B 0x00000000
    R GPIO2_GPIO_DEBOUNCINGTIME 0x0000000B 0x00000000
    R GPIO2_GPIO_CLEARDATAOUT 0x0000000B 0x00000000
    R GPIO2_GPIO_SETDATAOUT 0x0000000B 0x00000000
    R GPIO3_GPIO_REVISION 0x0000000B 0x50600801
    R GPIO3_GPIO_SYSCONFIG 0x0000000B 0x00000000
    R GPIO3_GPIO_IRQSTATUS_RAW_0 0x0000000B 0x00000000
    R GPIO3_GPIO_IRQSTATUS_RAW_1 0x0000000B 0x00000000
    R GPIO3_GPIO_IRQSTATUS_0 0x0000000B 0x00000000
    R GPIO3_GPIO_IRQSTATUS_1 0x0000000B 0x00000000
    R GPIO3_GPIO_IRQSTATUS_SET_0 0x0000000B 0x00000000
    R GPIO3_GPIO_IRQSTATUS_SET_1 0x0000000B 0x00000000
    R GPIO3_GPIO_IRQSTATUS_CLR_0 0x0000000B 0x00000000
    R GPIO3_GPIO_IRQSTATUS_CLR_1 0x0000000B 0x00000000
    R GPIO3_GPIO_IRQWAKEN_0 0x0000000B 0x00000000
    R GPIO3_GPIO_IRQWAKEN_1 0x0000000B 0x00000000
    R GPIO3_GPIO_SYSSTATUS 0x0000000B 0x00000000
    R GPIO3_GPIO_CTRL 0x0000000B 0x00000002
    R GPIO3_GPIO_OE 0x0000000B 0xFFF7FFFF
    R GPIO3_GPIO_DATAIN 0x0000000B 0x00000000
    R GPIO3_GPIO_DATAOUT 0x0000000B 0x00080000
    R GPIO3_GPIO_LEVELDETECT0 0x0000000B 0x00000000
    R GPIO3_GPIO_LEVELDETECT1 0x0000000B 0x00000000
    R GPIO3_GPIO_RISINGDETECT 0x0000000B 0x00000000
    R GPIO3_GPIO_FALLINGDETECT 0x0000000B 0x00000000
    R GPIO3_GPIO_DEBOUNCENABLE 0x0000000B 0x00000000
    R GPIO3_GPIO_DEBOUNCINGTIME 0x0000000B 0x00000000
    R GPIO3_GPIO_CLEARDATAOUT 0x0000000B 0x00080000
    R GPIO3_GPIO_SETDATAOUT 0x0000000B 0x00080000
    R MMC1_SD_SYSCONFIG 0x0000000B 0x00002015
    R MMC1_SD_SYSSTATUS 0x0000000B 0x00000001
    R MMC1_SD_CSRE 0x0000000B 0x00000000
    R MMC1_SD_SYSTEST 0x0000000B 0x00000000
    R MMC1_SD_CON 0x0000000B 0x00000600
    R MMC1_SD_PWCNT 0x0000000B 0x00000000
    R MMC1_SD_SDMASA 0x0000000B 0x00000000
    R MMC1_SD_BLK 0x0000000B 0x00000200
    R MMC1_SD_ARG 0x0000000B 0x00000000
    R MMC1_SD_CMD 0x0000000B 0x371A0000
    R MMC1_SD_RSP10 0x0000000B 0x00000000
    R MMC1_SD_RSP32 0x0000000B 0x00000000
    R MMC1_SD_RSP54 0x0000000B 0x00000000
    R MMC1_SD_RSP76 0x0000000B 0x00000000
    R MMC1_SD_DATA 0x0000000B 0x00000000
    R MMC1_SD_PSTATE 0x0000000B 0x01F70001
    R MMC1_SD_HCTL 0x0000000B 0x00000D10
    R MMC1_SD_SYSCTL 0x0000000B 0x000EF007
    R MMC1_SD_STAT 0x0000000B 0x20018040
    R MMC1_SD_IE 0x0000000B 0x307F0033
    R MMC1_SD_ISE 0x0000000B 0x00000000
    R MMC1_SD_AC12 0x0000000B 0x00000000
    R MMC1_SD_CAPA 0x0000000B 0x02E10080
    R MMC1_SD_CUR_CAPA 0x0000000B 0x00000000
    R MMC1_SD_FE 0x0000000B 0x00000000
    R MMC1_SD_ADMAES 0x0000000B 0x00000000
    R MMC1_SD_ADMASAL 0x0000000B 0x00000000
    R MMC1_SD_ADMASAH 0x0000000B 0x00000000
    R MMC1_SD_REV 0x0000000B 0x31010000
    R INTCPS_INTC_REVISION 0x0000000B 0x00000050
    R INTCPS_INTC_SYSCONFIG 0x0000000B 0x00000000
    R INTCPS_INTC_SYSSTATUS 0x0000000B 0x00000001
    R INTCPS_INTC_SIR_IRQ 0x0000000B 0x00000044
    R INTCPS_INTC_SIR_FIQ 0x0000000B 0xFFFFFF80
    R INTCPS_INTC_CONTROL 0x0000000B 0x00000000
    R INTCPS_INTC_PROTECTION 0x0000000B 0x00000000
    R INTCPS_INTC_IDLE 0x0000000B 0x00000000
    R INTCPS_INTC_IRQ_PRIORITY 0x0000000B 0x0000003F
    R INTCPS_INTC_FIQ_PRIORITY 0x0000000B 0xFFFFFFC0
    R INTCPS_INTC_THRESHOLD 0x0000000B 0x000000FF
    R INTCPS_INTC_ITR0 0x0000000B 0x00000302
    R INTCPS_INTC_MIR0 0x0000000B 0xFFFFFFFE
    R INTCPS_INTC_MIR_CLEAR0 0x0000000B 0x00000000
    R INTCPS_INTC_MIR_SET0 0x0000000B 0x00000000
    R INTCPS_INTC_ISR_SET0 0x0000000B 0x00000000
    R INTCPS_INTC_ISR_CLEAR0 0x0000000B 0x00000000
    R INTCPS_INTC_PENDING_IRQ0 0x0000000B 0x00000000
    R INTCPS_INTC_PENDING_FIQ0 0x0000000B 0x00000000
    R INTCPS_INTC_ITR1 0x0000000B 0x00000000
    R INTCPS_INTC_MIR1 0x0000000B 0xFFFFFFFF
    R INTCPS_INTC_MIR_CLEAR1 0x0000000B 0x00000000
    R INTCPS_INTC_MIR_SET1 0x0000000B 0x00000000
    R INTCPS_INTC_ISR_SET1 0x0000000B 0x00000000
    R INTCPS_INTC_ISR_CLEAR1 0x0000000B 0x00000000
    R INTCPS_INTC_PENDING_IRQ1 0x0000000B 0x00000000
    R INTCPS_INTC_PENDING_FIQ1 0x0000000B 0x00000000
    R INTCPS_INTC_ITR2 0x0000000B 0x00000010
    R INTCPS_INTC_MIR2 0x0000000B 0xFFFFFEEF
    R INTCPS_INTC_MIR_CLEAR2 0x0000000B 0x00000000
    R INTCPS_INTC_MIR_SET2 0x0000000B 0x00000000
    R INTCPS_INTC_ISR_SET2 0x0000000B 0x00000000
    R INTCPS_INTC_ISR_CLEAR2 0x0000000B 0x00000000
    R INTCPS_INTC_PENDING_IRQ2 0x0000000B 0x00000010
    R INTCPS_INTC_PENDING_FIQ2 0x0000000B 0x00000000
    R INTCPS_INTC_ITR3 0x0000000B 0x00000004
    R INTCPS_INTC_MIR3 0x0000000B 0xFFFFFFFB
    R INTCPS_INTC_MIR_CLEAR3 0x0000000B 0x00000000
    R INTCPS_INTC_MIR_SET3 0x0000000B 0x00000000
    R INTCPS_INTC_ISR_SET3 0x0000000B 0x00000000
    R INTCPS_INTC_ISR_CLEAR3 0x0000000B 0x00000000
    R INTCPS_INTC_PENDING_IRQ3 0x0000000B 0x00000004
    R INTCPS_INTC_PENDING_FIQ3 0x0000000B 0x00000000
    R INTCPS_INTC_ILR_0 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_1 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_2 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_3 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_4 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_5 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_6 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_7 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_8 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_9 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_10 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_11 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_12 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_13 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_14 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_15 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_16 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_17 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_18 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_19 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_20 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_21 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_22 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_23 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_24 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_25 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_26 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_27 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_28 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_29 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_30 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_31 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_32 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_33 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_34 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_35 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_36 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_37 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_38 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_39 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_40 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_41 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_42 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_43 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_44 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_45 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_46 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_47 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_48 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_49 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_50 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_51 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_52 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_53 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_54 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_55 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_56 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_57 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_58 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_59 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_60 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_61 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_62 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_63 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_64 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_65 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_66 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_67 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_68 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_69 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_70 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_71 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_72 0x0000000B 0x00000080
    R INTCPS_INTC_ILR_73 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_74 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_75 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_76 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_77 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_78 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_79 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_80 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_81 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_82 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_83 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_84 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_85 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_86 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_87 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_88 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_89 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_90 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_91 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_92 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_93 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_94 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_95 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_96 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_97 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_98 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_99 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_100 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_101 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_102 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_103 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_104 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_105 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_106 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_107 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_108 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_109 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_110 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_111 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_112 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_113 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_114 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_115 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_116 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_117 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_118 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_119 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_120 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_121 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_122 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_123 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_124 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_125 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_126 0x0000000B 0x000000FC
    R INTCPS_INTC_ILR_127 0x0000000B 0x000000FC
    

  • Not sure how to get a stack trace for you. Also, I am not sure if my register dump worked as I got a lot of "unable to save register ... " when I did the dump.
  • Alex,

    You may try to follow the steps (processors.wiki.ti.com/.../BIOS_FAQs ) to debug the crash issue.

    >>I have actually taken all of my networking code out of the program and the program still crashes
    Another option is probably just step by step to add the code for networking from working SPI program to narrow down the cause.

    Regards,
    Garrett
  • It was an issue with my MMU mapping. I copied the MMU stuff from my working NDK example .cfg file into my project and it is all working great!

    /* Define the base address of the 1 Meg page the peripheral resides in. */
    var peripheralBaseAddr = 0x40300000;

    /* Configure the corresponding MMU page descriptor accordingly */
    Mmu.setFirstLevelDescMeta(peripheralBaseAddr,
    peripheralBaseAddr,
    peripheralAttrs);


    /* Define the base address of the 1 Meg page the peripheral resides in. */
    var peripheralBaseAddr = 0x44e00000;

    /* Configure the corresponding MMU page descriptor accordingly */
    Mmu.setFirstLevelDescMeta(peripheralBaseAddr,
    peripheralBaseAddr,
    peripheralAttrs);


    /* Define the base address of the 1 Meg page the peripheral resides in. */
    var peripheralBaseAddr = 0x48000000;

    /* Configure the corresponding MMU page descriptor accordingly */
    Mmu.setFirstLevelDescMeta(peripheralBaseAddr,
    peripheralBaseAddr,
    peripheralAttrs);


    /* Define the base address of the 1 Meg page the peripheral resides in. */
    var peripheralBaseAddr = 0x48100000;

    /* Configure the corresponding MMU page descriptor accordingly */
    Mmu.setFirstLevelDescMeta(peripheralBaseAddr,
    peripheralBaseAddr,
    peripheralAttrs);


    /* Define the base address of the 1 Meg page the peripheral resides in. */
    var peripheralBaseAddr = 0x48200000;

    /* Configure the corresponding MMU page descriptor accordingly */
    Mmu.setFirstLevelDescMeta(peripheralBaseAddr,
    peripheralBaseAddr,
    peripheralAttrs);


    /* Define the base address of the 1 Meg page the peripheral resides in. */
    var peripheralBaseAddr = 0x48300000;

    /* Configure the corresponding MMU page descriptor accordingly */
    Mmu.setFirstLevelDescMeta(peripheralBaseAddr,
    peripheralBaseAddr,
    peripheralAttrs);


    /* Define the base address of the 1 Meg page the peripheral resides in. */
    var peripheralBaseAddr = 0x49000000;

    /* Configure the corresponding MMU page descriptor accordingly */
    Mmu.setFirstLevelDescMeta(peripheralBaseAddr,
    peripheralBaseAddr,
    peripheralAttrs);


    /* Define the base address of the 1 Meg page the peripheral resides in. */
    var peripheralBaseAddr = 0x4a100000;

    /* Configure the corresponding MMU page descriptor accordingly */
    Mmu.setFirstLevelDescMeta(peripheralBaseAddr,
    peripheralBaseAddr,
    peripheralAttrs);


    /* Define the base address of the 1 Meg page the peripheral resides in. */
    var peripheralBaseAddr = 0x4a300000;

    /* Configure the corresponding MMU page descriptor accordingly */
    Mmu.setFirstLevelDescMeta(peripheralBaseAddr,
    peripheralBaseAddr,
    peripheralAttrs);