TMS320C6678: PCIe linkup problem

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BR
Tsvetolin Shulev

Hi,

The PCIE_SERDES_STS = 0x201 -> (LOSDTCT1 = 1, we do not use this lane) (PLL LOCK = 1 , OK), this looks OK for one-lane connection.

In the PCIE RC side software, did you configure the PCIE x1 lane instead of x2 lane? You can refer to

5 PCIe Programming Example

This section includes the PCIe programming example for both RC mode and EP mode.

The two examples can be used on two devices to complete the write transaction from

RC to EP.

Example 5 Programming Example for RC Mode

/* Initialization sequence is as follows */

/* Suppose PCIe module is disabled (PCIESSEN=0) */

/* Enable power/clock domain of PCIe module */

enable_module (pciex_pdctl, pciex_mdctl); //please refer to PSC user’s guide

/* Set PCIe operation mode as RC */

/* First unlock boot configuration by setup KICK0&1 if locked before */

DEVSTAT[PCIESSMODE] = 0x10;

/* Program and enable SerDes PLL based on reference clock */

PCIE_SERDES_CFGPLL = 0x1C9; //reference clock assumed as 100MHz

/* Wait for PLL lockup */

While (PCIE_SERDES_STS[LOCK] !=1);

/* Disable link training */

CMD_STATUS[LTSSM_EN] = 0;

/* Setup configuration registers */

switch (lane_num) {

Case 1: //single lane

PL_LINK_CTRL[LINK_MODE] = 0x1; //enable x1 lane

Case 2: //two lanes

PL_LINK_CTRL[LINK_MODE] = 0x3; //enable x2 lanes

}

Also, does the FPGA and DSP use the same reference PCIE clock or not?

Regards, Eric

-In the PCIE RC side software, did you configure the PCIE x1 lane instead of x2 lane? You can refer to
Yes I configured 0x1 lane

-Also, does the FPGA and DSP use the same reference PCIE clock or not?
They use their own clock sources. C6678 use 100MHz clock and FPGA uses 125 MHz clock. Both evms do not have clock out so I used seperate clock sources. And I configured LINK_STAT_CTRL.COMMON_CLOCK_CFG = 0

Thanks!

From PCIE USER GUIDE:

If common clock architecture is not used, then the software driver must setup
appropriate bit (COMMON_CLK_CFG bit in LINK_STAT_CTRL register) in the PCI
Configuration registers to indicate so to the system. The number of training sequences
is significantly increased if reference clock is not shared between devices on a PCIe link.

Please also try if any of the following helps:
1) is it possible to configure FPGA using 100MHz internal reference clock
2) reduce to PCIE GEN1 on both sides
3) On TI PCIE RC, set LINK_STAT_CTRL.EXT_SYNC = 1 and PL_GEN2.NUM_FTS = 0xFF (you can change them in API calls or poke in the CCS memory window) before enabling the link training (CMD_STATUS.LTSSM_EN = 1).

Regards, Eric

Hi,

3) On TI PCIE RC, set LINK_STAT_CTRL.EXT_SYNC = 1 and PL_GEN2.NUM_FTS = 0xFF (you can change them in API calls or poke in the CCS memory window) before enabling the link training (CMD_STATUS.LTSSM_EN = 1).

- We tried this configuration but it didnt worked.

Do we have to push external clock to both sides to have same clock frequency? İs that the common approach?

Hi,

On the RC side, you used the TI C6678 EVM, correct? The C6678 PCIE uses the 100MHz on-board PCIE clock as the reference by default. It is possible to switch the clock source either from the on board crystal or from the PCIE AMC edge connector, this is controlled by FPGA on the EVM. We have trial of this by second bootloader (SBL) and PCIE in EP mode (where Linux PC is the PCIE RC and provides the clock from AMC edge connector).

We also have trial of both RC and EP with its own 100MHz clock. So, I think the best way for your trial is: try to configure the FPGA with 100MHz internal clock if possible.

Do we have to push external clock to both sides to have same clock frequency? İs that the common approach?=====> From Keystone PCIE user guide, the PCIE only accept 100MHz clock. Does the FPGA also accept 100MHz clock? Also, the RC side you need to change FPGA control to let the clock coming from AMC edge connector instead of on-board.

Also, let us know if GEN1 works for this?

Regards, Eric

Any news?

Regards, Eric

Hi we are thinking about hardware preperation for external clock source.
If we apply 125 Mhz clock to C6678 from AMC, does it work? What serdes configurations should we do for this?

We used 100MHz for the C6678 EVM, the 125MHz should work as well. From PCIE user guide, please look at 2.3.3 Reference Clock Multiplication and PCIe SerDes Configuration Register (PCIE_SERDES_CFGPLL).

Regards, Eric

Hi we are at the same configuration ( DSP = 100Mhz, FPGA = 125 Mhz). WE just made a hardware improvement and now sometimes ltssm state becomes 6. Actually it always changes between 1, 2 and 6 now. Does this have any meaning? Any suggestions ?

Thank you.