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RTOS/TDA2EVM5777: How to ensure data write completion on System_BitstreamBuffer

Part Number: TDA2EVM5777

Tool/software: TI-RTOS

Hello,

We created a link that received data from Encoder Link.
Since Encoder Link outputs bitstream in its output queue, we are using System_BitstreamBuffer in our input queue.

In our link when we receive SYSTEM_CMD_NEW_DATA, we get the data pointer address and data size from the System_BitstreamBuffer.
Before we are passing the address and size to NSP for network sending directly, this is working and data seems to be completely written before NSP sends data through the network interface.

Now, however, we need to compute the checksum prior to sending the data.
The problem is that it seems System_BitstreamBuffer notifies data address and data size while still writing the actual data at the time of SYSTEM_CMD_NEW_DATA.

This results to our checksum computation to produce incorrect result.

Refer to memory dump below:

■ data during SYSTEM_CMD_NEW_DATA

0000   00 00 00 01 21 9a 01 3a 74 41 d7 00 00 03 00 00
0010   03 00 00 03 00 00 03 00 00 03 00 00 03 00 00 03
0020   01 69 fc 5c 31 c2 5d f3 79 64 d0 c7 1a fe f8 0c
0030   e2 99 d4 df 83 eb ec 11 0a 51 79 26 e1 db 08 12
0040   00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0050   00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0060   00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0070   00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0080   00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0090   00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

■ Actual data send after passing to NSP

0000   00 00 00 01 21 9a 01 3a 74 41 d7 00 00 03 00 00
0010   03 00 00 03 00 00 03 00 00 03 00 00 03 00 00 03
0020   01 69 fc 5c 31 c2 5d f3 79 64 d0 c7 1a fe f8 0c
0030   e2 99 d4 df 83 eb ec 11 0a 51 79 26 e1 db 08 12
0040   d9 cd 6b a0 bc 10 39 e4 a5 e6 6b a3 e4 bb e8 7c
0050   c9 2b a8 96 44 42 80 3f 4e 8a 90 2e 6b 3b 45 1b
0060   d3 97 6d de 4c de b3 0f 99 96 0b 1a c6 ab 77 bb
0070   29 12 63 ee f5 c6 ae 3f 5b d8 f2 7b 4d f4 bf 5f
0080   d6 ac 44 ba 0a 2d a1 2e 2f 4e d9 54 a0 70 f5 dc
0090   3b b1 b9 15 1a b2 98 73 05 d4 53 c3 ff 21 2a 67

Since we need to wait for the complete data in order to compute the correct checksum, may we ask the following:
- How can we ensure write completion on a System_BitstreamBuffer?
- Could you provide the correct APIs? We tried to find it in xCHM but cannot find it?

 

  • This issue is resolved by flushing and invalidating the cache.
    Apparently, it is required when data is being passed from one core to another core.
    In the above discussion, Encoder link is in IPU1_0 and the link processing the data is in A15.

    This is documented in the following:

    IPC Link API

    IPC Links do NOT take care of the below
    o Cache operations on the contents of the buffer
    o Every processing link writing data to a buffer via CPU is supposed to flush the contents of the buffer out of cache before passing the buffer pointer to the next link
    o Every processing link reading data from a buffer via CPU is supposed to invalidate the contents of the buffer before using
    o When buffer data is generated / read by HWA or EDMA then the processing link need not do flush / invalidate operations on the buffer
    o Since such information is not available to IPC link, IPC link will not touch the data pointed to by a buffer and neither will it do any cache operation on the data pointed to by a buffer
  • Hi Normal,

    Yes, that's correct IPC link does not take care of cache operation, it does not even know if the buffer is cached or not.. IPC link just sends a pointer to the link on remote core. It is the responsibility of individual link to do cache operations based on the buffer it is getting..

    Regards,

    Brijesh