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AM5726: RESETn release time

UNA
Mastermind 7980 points
Part Number: AM5726
Other Parts Discussed in Thread: AM5728

Hi,

I have question about the AM5728 power up sequence. This question is related to the following thread.


I think that RESETN pin is high before VDDA33V_USB and VDDSHV8 in the AM572xEVM. It seems that It violates the power-up sequence of AM572x.
So, RESET_OUT of PMIC should be connected to RESETN in addition to PORZ and RTC_PORZ. Is my thinking correct?

Best regards,
H.U

  • 0
    TI__Guru**** 393215 points

    Hi,

    H.U said:
    I think that RESETN pin is high before VDDA33V_USB and VDDSHV8 in the AM572xEVM.

    How did you reach this conclusion? Did you measure it? Can you post the screenshot?

  • 0 in reply to Biser Gatchev-XID
    Mastermind 7980 points
    Hi Biser,

    Although it is obvious if you see the schematic of the AM 572xEVM, the output of the AND gate (U10) is connected to RESETN, if JTAG is not connected, this output goes High simultaneously with the ramp up of VDD_3V3_SP.
    Because, the CPU_RESETn and EMU_RSTn which are input signals to AND gate(U10) are pulled up by VDD_3V3_S.

    Best regards,
    H.U
  • 0 in reply to UNA
    TI__Mastermind 42545 points

    Hi,

    I'm going to have to do a little research on this one. Generally the POR will supersede the warm reset RESETn and the only requirement on RESETn is that it can't be driven high until the IO voltage associated with that input is present. I see that the requirement in the data manual states that RESETn and PORz should remain low until all power supplies are stable. I will need to check with the design team on why this requirement is necessary. 

    Regards, Bill

  • 0 in reply to Bill Taboada
    TI__Mastermind 42545 points
    Hi,
    I have discussed this with the design team and they pointed out the information in i862 of the errata. That errata states that only PORz should be used to reset the part. The consensus is that note 11 in the data manual is incorrect and that RESETn should be set high as soon as the IO voltage for the RESETn buffer is present.
    Regards, Bill
  • 0 in reply to Bill Taboada
    Mastermind 7980 points

    Hi Bill,

    Thank you for your reply. but please let me reconfirm. 

    Are you say that there is no problem if RESETN goes high before the VDDA33V_USB and VDDSHV8 ramp up?,
    and does RESETn and PORZ should not be set high at the same time?

    Best regards,
    H.U

  • 0 in reply to UNA
    TI__Mastermind 42545 points
    Hi,
    That is correct. RESETN can go high as soon as the supply rail for the buffer IO is present. Since it is pulled to that voltage for the EVM, it will meet that condition. PORz should meet the sequencing requirements and the conditions in note 11 of the data manual but RESETN can go high earlier. The PORz will hold the part in reset even though RESETN has gone high.
    Regards, Bill
  • 0 in reply to Bill Taboada
    Mastermind 7980 points

    Hi Bill,

    Please let me ask another question.
    Is it OK if PORZ and RTC_PORZ go high at the same time?
    In EVM, RESET_OUT of PMIC is connected to PORZ and RTC_PORZ of AM572x.

    Best regards,
    H.U

  • 0 in reply to UNA
    TI__Mastermind 42545 points

    Hi,

    RTC_PORz can go high if the conditions in notes 9 & 10 are met. If PORz and RTC_PORz are tied together then the conditions in notes 9, 10 & 11 must all be met before these signals go high.  There is no dependency shown between PORz going hign and RTC_PORz going high so they may be tied together but all conditions must be met for both signals.

    Regards, Bill