• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 99 subscribers
  • Views 408 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TVP5146 decoder on custom board

Sid
Genius 4530 points

Other Parts Discussed in Thread: TVP5146, TMS320DM6467

Hi,

I am trying to implement the functionality of a TVP5146 decoder on a custom board consisting of TMS320DM6467 Davinci processor.

I am giving a CVBS signal as input, and configuring the decoder using I2C. On configuration, I can see 27 MHz clock on Decoder clkout pin and also some data on the decoder output pins which , i suppose , is an indication that the decoder has been successfully configured.

Thereafter, I configure the VPIF controller by writing its control registers, and I wait for the data to be written in to the DDR SDRAM. But the DDR does not get written to by VPIF at all. I have individually checked the DDR by writing an array of data into it and reading the data into a file. The data gets read back successfully which means DDR controller/configuration is correct.

It seems the VPIF is not getting configured correctly to write into the DDR. I have done all the configurations as suggested in the VPIF user guide. AM I missing something in the configuration due to which Input channel 0/channel 1 does not get configured?

BTW, I am using CCS3.3  and dont have access to a Linux machine presently.

Thanks in advance.[:)]

Sidharth

  • 0
    TI__Mastermind 37340 points

    I would recommend you try to get a Linux Host machine soon; working VPIF Linux drivers are provided in the DVSDK; also DM6467 reference EVM uses a similar TVP part which also comes with a Linux driver.  Additionally, there are Linux drivers for other DaVinci platforms which use TVP5146 which you can leverage.  As you can see, you are missing out on a good amount of source code to help you achieve your goal by not moving to Linux..

  • 0 in reply to Juan Gonzales
    Genius 4530 points

    Thanks Juan,

    I have been successful in sorting out the issues I mentioned in my earlier post by modifying some register values. I am getting the video output successfully.

    Basically, my present application is a basic loopback application wherein I feed a video input to the decoder, loopback it  and DDR and take the output from encoder and flash it on TV screen(CVBS output).

    The video output I get , though, contains a patch of horizontal noise like lines in the middle of the screen which slowly shift downwards.

    Is this problem related to SYNC, or some other issue? I am using embedded sync.

    Thanks and regards,

    Sidharth

  • 0 in reply to Sid
    TI__Mastermind 37340 points

    what resolution are you working with (input and output), since you mentioned CVBS output, I assume NTSC or PAL, is this correct?  noise lines are normally seen when either syncs are off, or DDR2 bandiwth is bieng pushed to the limit.  I would not expect DDR2 bandwidth issues if you are working with non-HD resolutions... perhaps in HD resolutions depending on what else is going on in the system; for example capture, deinterlace, resize, and display for HD resolutions, all going on in parallel may push DDR2 bandwidth..

  • 0 in reply to Juan Gonzales
    Genius 4530 points

    Hi Juan,

    I am using PAL. Also I am working with SD resolution so I dont think the DDR2 bandwidth is being exceeded.

    Regarding whether syncs are off, I am using embedded sync and I have rechecked to make sure that I have enabled them.

    I wanted to ask whether something related to hardware can cause this problem, like some faulty settings ,etc?

    Thanks for your help,

    Sidharth

  • 0 in reply to Sid
    TI__Mastermind 41665 points

    Sidharth Garde said:
    The video output I get , though, contains a patch of horizontal noise like lines in the middle of the screen which slowly shift downwards.

    This description sounds like it could be a cache coherency issue, in your loopback application are you doing any work on the frame buffers with the CPU (for example copying from capture to display with the CPU)? Usually this coherency would be handled by Linux on the ARM but since you mention you are working with CCS it is possible you may have a coherency issue where the CPU is seeing data in its cache that has since been updated externally by the VPIF, or that the VPIF is not seeing data that is still cached in the CPU.

    It is possible that this could be a hardware problem but that is relatively unlikely as long as your signals are all clean, I have also seen horizontal line noise of some types when the horizontal sync is not clean enough. If you could post a picture of the output with the noise that may give some better ideas.