RTOS/AMIC110: PTCP compensation method in Profinet

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Thank you Biser.
I think there is another problem need to be clarified.
According to the datasheet, AMIC110 doesn't support eCAP.
I am not sure if eCAP and EDMA are only used for "fast" compensation.
But ptcpEnableSlowCompensation is set to 0, which means eCAP is used in Profinet project. I don't know if it can work correctly.

Nathan,

We validated IRT mode in the last release on AMIC110 EVM. Trying to clarify the eCAP support on AMIC110, and will share you the details of PTCP implementation shortly.

Regards,
Garrett

Nathan,

AMIC110 does not support the SoC-level eCAPs but the PRU-ICSS eCAP sub-module is still supported, see section 1.1 in datasheet:

Peripherals Inside the PRU-ICSS:

– One UART Port With Flow Control Pins,

Supports up to 12 Mbps

– One Enhanced Capture (eCAP) Module

Regarding the PTCP clock compensation method:

PRU firmware receives and forwards Sync and follow up frames from dedicated buffers. Sync ISR triggers clock synchronization. PTCP design for SoC platforms such as AM335x and AM437x uses ECAP, EDMA, IEP chain for clock synchronization.

         MasterT = Torg + line_delay
         LocalT = RXSFD of received sync frame

deltaT is calculated as
         deltaT=MasterT-LocalT

Filtering is applied on deltaT to get clock drift

         adjDeltaT = simple moving average of deltaT values
Over one sync interval, the IEP counter is compensated by adjDeltaT.

Regards,

Garrett

Hi Garrett,

Thanks for your explain of PTCP compensation, it's very helpful and clear.

I was confused because the target register of reconfiguring eCAP seems in SoC level in stead of PRU-ICSS.

The source code in project:

void PN_PTCP_reconfigEcap(PN_Handle pnHandle, int32_t period)

{

   uint32_t pwmssBaseAddr = (pnHandle->pnPtcpConfig)->ecapPwmssBaseAddr;

   /* Stop the counter */

   HW_WR_FIELD16(pwmssBaseAddr + CSL_ECAP_ECCTL2,

                 CSL_ECAP_ECCTL2_TSCTRSTOP, CSL_ECAP_ECCTL2_TSCTRSTOP_STOPPED);

   /* Set TSCTR to 0 */

   HW_WR_FIELD32(pwmssBaseAddr + CSL_ECAP_TSCTR,

                 CSL_ECAP_TSCTR_TSCTR, CSL_ECAP_TSCTR_TSCTR_RESETVAL);

   /* CRYPTO: check whether we can use shadow registers or not?

      set the period */

   HW_WR_FIELD32(pwmssBaseAddr + CSL_ECAP_CAP1,

                 CSL_ECAP_CAP1_CAP1, (((period / 5) / 2) - 1));

   /* Clear the Period Event Flag      0x00c1*/

   HW_WR_FIELD16(pwmssBaseAddr + CSL_ECAP_ECCLR,

                 CSL_ECAP_ECCLR_INT, CSL_ECAP_ECCLR_INT_CLEAR);

   HW_WR_FIELD16(pwmssBaseAddr + CSL_ECAP_ECCLR,

                 CSL_ECAP_ECCLR_PRDEQ, CSL_ECAP_ECCLR_PRDEQ_CLEAR);

   HW_WR_FIELD16(pwmssBaseAddr + CSL_ECAP_ECCLR,

                 CSL_ECAP_ECCLR_CMPEQ, CSL_ECAP_ECCLR_CMPEQ_CLEAR);

   /* Start the counter */

   HW_WR_FIELD16(pwmssBaseAddr + CSL_ECAP_ECCTL2,

                 CSL_ECAP_ECCTL2_TSCTRSTOP, CSL_ECAP_ECCTL2_TSCTRSTOP_FREE_RUNNING);

}

Regards,

Nathan

Hi Nathan,

>>the target register of reconfiguring eCAP seems in SoC level in stead of PRU-ICSS
It's true that the target register of reconfiguring eCAP is in SoC level.

Currently there is no plan to support SOC eCAP functions on AMIC110. However, your inquiry has initiated a discussion to review this decision and we will update this post once the discussion is complete.

Regards,
Garrett