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AM5716: GPMC CS0 address space

Kzk
Genius 5785 points

Part Number: AM5716

Hello,

I'd like to understand the space that can be used of GPMC CS0. Is my understanding correct?

After booting from other than GPMC, the application can not use the lowest 1-MiB memory space [0x0000 0000 - 0x000F FFFF] of CS0. On the other hand, in booting from GPMC, this space can be used. In NAND boot, boot from 0x0000 0000. In XIP boot, MPU ROM code jumps to address 0x0800 0000 instead of 0x0000 0000.

I'm referring to the following document.

AM 571 x TRM (SPRUHZ7G)
2.2 L3_MAIN Memory Map
33.3 Device Initialization by ROM Code

Regards,
Kazu

  • 0
    TI__Guru**** 393215 points
    Hi,

    Section 2.2 from the TRM states:

    Boot space:
    - When booting from the on-chip ROM with the appropriate external sys_boot pin configuration, the lowest 1-MiB memory space [0x0000 0000 –
    0x000F FFFF] is redirected to the on-chip boot ROM address space [0x4000 0000–0x400F FFFF].
    - When booting from the GPMC, the memory space is part of the GPMC address space. At reset, the 0x0000 0000 address is available on chip select
    0 (CS0) for a memory size of 16MiB.
  • 0 in reply to Biser Gatchev-XID
    Genius 5785 points

    Hello Biser,

    Thank you for your quick reply.

    Biser Gatchev-XID said:
    - When booting from the on-chip ROM with the appropriate external sys_boot pin configuration, the lowest 1-MiB memory space [0x0000 0000 – 0x000F FFFF] is redirected to the on-chip boot ROM address space [0x4000 0000–0x400F FFFF].

    Does it mean that my application of CA15 can't access the lowest 1-MiB memory space of CS0 if AM5716 boots from other than GPMC? How about CM4 and C66?

    Is MMU used for redirecting at boot time? If so, I think that my applications can access this space by changing the MMU settings.

    Please give me some advice.

    Regards,
    Kazu

  • 0 in reply to Kzk
    TI__Guru**** 393215 points
    I have asked the factory team to comment. They will post here.
  • 0 in reply to Biser Gatchev-XID
    TI__Mastermind 46460 points

    Kazu,

    I believe this restriction exists during the earliest part of the boot process when the ROM bootloader first executes but you also want to use GPMC with CS0.  At this initial boot time, the bottom 1MB of the L3 address map that would normally be allocated to GPMC CS0 is remapped for use by the ROM bootloader.  After the boot process is complete and your application is loaded, the MMU can then be reprogrammed to use all of the memory present at GPMC CS0.

    Why are you concerned with this low-level behavior?  All of this should be managed by the code provided as part of our PROC-SDK.  Specifically, are you running Linux?  This will be managed by Uboot.

    Tom

  • 0 in reply to Tom Johnson 16214
    Genius 5785 points

    Hello Tom,

    Thank you for your support.

    Tom Johnson 16214 said:
    Why are you concerned with this low-level behavior?  All of this should be managed by the code provided as part of our PROC-SDK.  Specifically, are you running Linux?  This will be managed by Uboot.

    On my board, a SRAM (several Mbytes) is connected to CS0 of GPMC. CA15 can not access address 0 because CS0 doesn't become active. But it seems to be able to access next 1 MB (0x0010 0000 - 0x0020 0000).

    Could you tell me how to do change method if I need to set MMU configuration? I'm using my own RTOS.

    I think that SBL_MMUInit function in sbl_startup.c of PDK looks like reallocating address 0 (physical address 0 to virtual address 0). But I can't find such a description in GEL file.

    Regards,
    Kazu

  • 0 in reply to Kzk
    TI__Genius 15510 points
    What you can do is set up the MMU with a physical address in the SRAM and configure a virtual address of 0.

    Steve K.