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AM3354: I2C Master NAK issue

g.f.
Guru 15520 points

Part Number: AM3354

Hi,

I have questions about AM335x I2C.

AM335x I2C is master and external RTC are connected as I2C slave.
When I2C master is receiver, I understand that master will send
NACK after receiving last data byte (when DCOUNT register value is 1).
But at my customer's board, somtimes AM335x I2C master send NACK before the last data byte receive phase.
Why AM335x I2C master send NACK before last data byte phase?
What kind of factors can be considered?

best regards,
g.f.

Send NACK at unintended timing

  • 0
    TI__Guru**** 393215 points
    Hi,

    What software is this? Linux, RTOS, other?
  • 0
    TI__Guru 65405 points
    Hi G.F.,

    There are several conditions that lead to the generation of a NACK:
    1. The receiver is unable to receive or transmit because it is performing some real-time function and is not ready to start communication with the master.
    2. During the transfer, the receiver gets data or commands that it does not understand.
    3. During the transfer, the receiver cannot receive any more data bytes.
    4. A master-receiver is done reading data and indicates this to the slave through a NACK.
    You should check each one of these conditions.
    For more details about I2C bus refer to:
    www.ti.com/.../slva704.pdf

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    Guru 15520 points
    Hi Biser and Tsvetolin,

    Thank you for the reply.

    This question is from my customer, and their OS is WinCE7.

    I understood that there are several condition for generating NACK.
    The condition 1-3 which you attached to above post, isn't I2C slave generate the NACK?
    My understanding is that I2C master will generate NACK in condition #4 only, am I wrong?

    My customer are setting DCOUNT to 16, so usually AM335x I2C master will receive 16 byte
    from the I2C slave. But sometimes NACK are generated before the last data receive.
    They checked the ROVR bit field of I2C_IRQSTATUS register, it's set to Zero(Normal Operation).
    There are no overrun so that we don't know why AM335x I2C master can't receive all data.

    Are there anythingelse we should check?

    best regards,
    g.f.
  • 0 in reply to g.f.
    Guru 15520 points
    Hi Biser and Tsvetolin,

    This problem have been solved.
    My customer was changing DCOUNT register value after Start condition.
    After they fixed their software, the issue didn't came up so far.

    But I have other question about AM335x I2C.
    I will close this post, and make new post for other question
    because other question doesn't related to this issue.

    best regards,
    g.f.