DRA756: DRA756

Mandar Pande

Part Number: DRA756

Hello,

What are the ways of controlling the Coretx-M4 core in the IPUx subsystem through an application running on the MPU Cortex-A15 ?

In my application, I am trying to implement a fail-safe mechanism, where the A15 core is alerted if the M4 core fails.

How can I implement such a mechanism?

As an additional information, I will be running Linux on the A15 cores and RTOS on the M4 core. I will boot M4 core first using the Early Boot and Late Attach mechanism.

Thanks in Advance,

Mandar

over 8 years ago

0 Yordan Kamenov over 8 years ago

TI__Mastermind 42515 points

Hi Mandar,

I have forwarded your question to an expert for comment.

Regards,
Yordan

0 Angela Stegmaier over 8 years ago

TI__Expert 3640 points

Hi Mandar,

Can you let us know what SDK you are using?

If by controlling you are looking for means of communication with the remote core, then for sending messages between cores you can have a look at the IPC3.x package. This is typically included with the SDKs and runs on top of SYS/BIOS on the remote core. You can find information on IPC3.x here:
processors.wiki.ti.com/.../IPC_3.x

Additionally, Linux remoteproc has an error recovery feature for the remote cores which will reload and restart remote cores after it detects fatal errors. The IPC3.x wiki has information on error recovery when using IPC3.x here:
processors.wiki.ti.com/.../IPC_Slave_Error_Recovery

Thanks,
Angela

0 Mandar Pande over 8 years ago in reply to Angela Stegmaier

Prodigy 60 points

Hi,

Thank you for your answer. It was really helpful.

Can you suggest an SDK for DRA7xx series which will have support for this IPC3.x?

Also, is there anything at the firmware level that I can do in order to implement a failsafe strategy?

Thanks,

Mandar

0 Angela Stegmaier over 8 years ago in reply to Mandar Pande

TI__Expert 3640 points

Hi Mandar,

You can find the available SDKs for DRA7X here:
www.ti.com/.../processor-sdk-dra7x

All of them support IPC3.x.

Thanks,
Angela

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DRA756: DRA756