AM5728: DDR3 LSB bit swapping

Colin Hankins94

Part Number: AM5728

Hi,

I've seen numerous posts referencing this topic, and how all the bits within a byte lane can be swapped except for the LSB due to HW leveling. Is this documented anywhere?

I looked at the schematic checklist and it does not specify the LSB within a byte lane needing to match:

Data bit swapping within the data byte is allowed. The PHY is implemented such that this does not impact leveling. Bit swapping is not allowed for any other group of signals, including ADDR and CNTL

processors.wiki.ti.com/.../AM57xx_Schematic_Checklist

So can we swap the LSB or not?

Regards,

Colin

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

The DDR experts have been notified. They will respond here.

0 sivak over 7 years ago

TI__Genius 9655 points

Colin

As is mentioned in the AM57x schematic checklist, the data bits within a given Byte group can be swapped including the prime bit i.e. the LSB. The DDR PHY implements a logic to OR all the data bits of the given byte to check for the DQ response from the DDR. Therefore, the prime bit i.e. the LSB also can be swapped.

Let us know if you have any additional questions.

Regards, Siva

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AM5728: DDR3 LSB bit swapping