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AM4378: ADC0 clock frequency

Part Number: AM4378

I have noticed in the TI AM437x TRM (spruhl7h.pdf), section 12.2.2 MagneticCard Reader Clock and Reset Management lists a requirement for ADC1 that the frequency of ocp_clock must be greater than or equal to six times the frequency of adc_clk.

It appears that this requirement is not present in section 11.2.2 TSC_ADC (ADC0) Clock and Reset management.  Does the same adc_clk frequency requirement exist for ADC0 as it does for ADC1?

Thanks,

Stuart

  • The factory team have been notified. They will respond here.
  • Yes, ADC0 has the same requirement.

    The ADC0/Touch Screen chapter was initially created for a previous device and copied to the AM437x TRM.  The ADC1/Magnet Card Reader chapter was created at a later date specifically for AM437x. I suspect the original author was not aware of this requirement, therefore it was not included. Thanks for highlighting this detail so we can get it added to the ADC0/Touch Screen chapter of both device TRMs.

    I recently found another ADC clock related requirement which needs to be described in the TRM. The accuracy of the ADC may be slightly compromised if operated with an ADC clock that is too slow. This occurs when leakage paths bleed charge from internal capacitors before the charge sharing successive approximation ADC completes the conversion after the input voltage is sampled. At this time, I do not know the minimum frequency which should be used for the AM437x ADCs. I will update this post when this information is available.

    Regards,
    Paul