TMS320C6678: Questions on Hyperlink and SRIO

Hi,

SRIO Gen 1 vs SRIO Gen 2 (how much effective bandwidth increased compare to SRIO Gen 1 when SRIO Gen 2 is used?

SRIO Gen 2 supports up to 5Gbaud per lane, while SRIO GEN1 supports up to 3.25 Gbaud per lane, so if you connect RapidIO gen1 and RapidIO gen2 interfaces you loose about 1.57 Gbaud per lane.

What is latency of hyperlink communication?

This threads provides information for latency of Hyperlink communicaion:
e2e.ti.com/.../300286
also e2e.ti.com/.../253039

what is error handling of hyerplink, any re-try process?

See Section 1.4 Functional Block Diagram of the Hyperlink user guide: www.ti.com/.../sprugw8c.pdf
It describes the following:
"The PLS module on the egress side encodes the MAC transmit data using a GFP 32/33 encoding, adding a nine-bit Error Correction Code ECC), then scrambling the data before sending it to the SerDes. On the ingress side, the PLS aligns the serial bit stream to the 36-bit symbol boundary, identifies the synchronizing codes, descrambles the data, aligns to the ECC boundary, performs the ECC correction, decodes data using GFP 33/32, and presents the resulting data to the MAC receiver"

Hyperlink access address size up to 256MB, does it mean 8 cores could access 8 different segments which each segment size is 256MB

Hyperlink is a point-to-point communication. Each of this cores can use this Hyperlink access address size at different times.

Best Regards,
Yordan

Hi,

Actually Garrett has answered on the other thread you've opened with the same questions as in your last post:
e2e.ti.com/.../2479458

Monitor that discussion about SRIO throughput. I am closing this thread for now.

Best Regards,
Yordan