Hi,
Our custom board with micrel KSZ8895, currently ping failed.
U-Boot# setenv ipaddr 192.168.1.1
U-Boot# ping 192.168.1.10
ksz8895_startup
ksz8895_startup
link up on port 0, speed 100, full duplex
Using cpsw device
ping failed; host 192.168.1.10 is not alive
U-Boot# mii info
PHY 0x01: OUI = 0x0885, Model = 0x05, Rev = 0x00, 10baseT, HDX
PHY 0x02: OUI = 0x0885, Model = 0x05, Rev = 0x00, 10baseT, HDX
PHY 0x03: OUI = 0x0885, Model = 0x05, Rev = 0x00, 100baseT, FDX
PHY 0x04: OUI = 0x0885, Model = 0x05, Rev = 0x00, 10baseT, HDX
PHY 0x05: OUI = 0x0885, Model = 0x05, Rev = 0x00, 10baseT, HDX
PHY 0x06: OUI = 0x0100, Model = 0x00, Rev = 0x04, 10baseT, HDX
PHY 0x07: OUI = 0x0180, Model = 0x00, Rev = 0x00, 10baseT, HDX
PHY 0x0E: OUI = 0x0180, Model = 0x00, Rev = 0x00, 10baseT, HDX
PHY 0x0F: OUI = 0x0100, Model = 0x00, Rev = 0x04, 10baseT, HDX
PHY 0x16: OUI = 0x2100, Model = 0x08, Rev = 0x00, 10baseT, HDX
PHY 0x17: OUI = 0x01C0, Model = 0x00, Rev = 0x00, 10baseT, HDX
PHY 0x1E: OUI = 0x2200, Model = 0x08, Rev = 0x04, 10baseT, HDX
PHY 0x1F: OUI = 0x2200, Model = 0x08, Rev = 0x04, 10baseT, HDX
only PHY 0x06 can read the correct info
U-Boot# mdio read cpsw 6 0
Reading from bus cpsw
PHY at address 6:
0 - 0x95
0x95 is chip family id.
But our hardware design address is 3, so I modify phy_addr to 3.
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 3,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_addr = 1,
},
};
U-Boot# mdio list
cpsw:
3 - Micrel KSZ8895/KSZ8864 <--> cpsw
We have already ported KSZ8895 driver to uboot. Uboot print info is as follows.
U-Boot 2014.10-dirty (Feb 26 2018 - 15:20:20)
Watchdog enabled
I2C: ready
DRAM: 512 MiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
SF: Detected W25Q64CV with page size 256 Bytes, erase size 4 KiB, total 8 MiB
*** Warning - bad CRC, using default environment
Net: phy_init
phy_init
phy_micrel_init
phy_micrel_init
ksz8895_write_smireg
ksz8895_write_smireg
ksz8895_config
ksz8895_config
cpsw, usb_ether
Hit any key to stop autoboot: 0
I already defined CONFIG_PHY_MICREL, and we use RMII mode.
#define CONFIG_PHY_MICREL
writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_RMII;
I also modify mux:
static struct module_pin_mux rmii1_pin_mux[] = {
{OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
{OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */
{OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */
{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */
{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */
{OFFSET(mii1_rxdv), MODE(1) | RXACTIVE}, /* RMII1_RXDV */
{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_refclk */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
configure_module_pin_mux(rmii1_pin_mux);
Any help will be appreciated, thanks.
