Hello, I was wondering how the Teranet bus handles when DSP cores are trying to access different high-speed serial ports at the same time. For example, let's say that DSP Core 0 is using PCIe port 1 and DSP Core 1 is using PCIe port 2 and ARM Core 0 is using the 10Gb Ethernet. Does the cores have to share the bus or can each core operate independently allowing simultaneous access to each port? For example, can DSP Core 0 perform a PCIe write on port 1 at the same time that DSP Core 1 is doing a PCIe write on port 2.
Thanks,
Joe
