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TDA2P-ABZ: Inconsistent Technical Reference Manual TDA2Px

Part Number: TDA2P-ABZ

Hi Team,

Could you please answer my customer question?

I found inconsistent memory descriptions in the technical reference manual (Literature Number: SPRUIF0A May 2017–Revised November 2017):

Page 471, 2nd line (marked red):  512KiB à 512MiB (0x1FFF_FFFF= 536870911)???

  • The following address areas (marked blue) in Table 2-9, I can’t find them in Table 2-1 (see below)
  • 0x00000000 – 0x1FFFFFFF
  • 0x24000000 – 0x3FFFFFFF
  • 0x40300000 -  0x41FFFFFF
  • 0x44000000 – 0x54FFFFFF
  • 0x56000000 – 0xDFFFFFFF

Maybe the link to Table 2-1 or the addresses are not correct. I hope you can help me.

Thanks,

Needhu

  • Hi,

    The first entry in IPU memory map looks like a bug in TRM: L3_MAIN map 0x0000_0000 0x1FFF_FFFF 512KiB.
    Instead of KiB, it should be MiB.
    For the entries in IPU memory map which are marked as See Table 2.1 you should see L3 map. There can be multiple entries in L3 map for one entry marked like this.

    Regards,
    Rishabh
  • Hi Rishabh,

    Thank you for your quick reply. Could you please clarify,

    • For Example: IPU memory 0x56000000 – 0xDFFFFFFF correlates with GPU memory in L3 memory map. So GPU and IPU have read/write access to the same address area?
    • For Example: IPU memory 0x40300000 - 0x41FFFFFF correlates with Reserved memory areas (0x40380000) in L3 memory map. So the IPU is able to reads/write to “Reserved” region?

    Thanks.
    -Needhu
  • Hi Needhu,

    Wherever there is a correlation with reserved area it means that area is reserved when accessed by L3 and IPU both. Similarly GPU memory can be viewed by IPU and L3 at the particular location.

    Regards,
    Rishabh