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TMDXIDK5718: QSPI in memory mapped mode

Part Number: TMDXIDK5718
Other Parts Discussed in Thread: AM5718

Hi

I read the TRM about the QSPI module on my AM5718 processor and I also studied the qspi example
provided with the platform delevopment kit (PDK) V1.08, included in SDK V4.01.00 for TI-RTOS.

I try to read and write from/to the QSPI NOR flash included in the IDK5718 EVM.
To access flash devices via QSPI the TRM recommends to use the memory mapped mode of the QSPI module.

The TRM (spruhz7g, chapter 24.5.4.1.2, page 5851) says about memory mapped mode:

====================================================
A read sequence is converted into the following actions:
1. SPI chip-select goes active.
2. Read command byte is issued.
3. 1 to 4 address bytes, which correspond to the first address supplied, are issued.
4. 0 to 3 dummy bytes are issued, if “fast read” is supported.
5. Data bytes are read from the external SPI flash memory.
6. SPI chip-select goes inactive.
For linear addressing mode, action 5 is repeated until the byte count to be transferred reaches zero.
A write sequence is identical to a read sequence, except that a write sequence does not use dummy
bytes.
====================================================

At the moment I'm not able to send more than 32Bits of data to the flash device before the chip select
signal automatically returns to inactive state (step 6 above). How can I achieve that step 5 is repeated
for more than four bytes?

I tried the following to write to memory mapped qspi region:

*(uint8_t *)pDst = *(uint8_t *)pSrc; // -> Step 5 puts 8 bits on the data line
*(uint16_t *)pDst = *(uint16_t *)pSrc; // -> Step 5 puts 16 bits on the data line
*(uint32_t *)pDst = *(uint32_t *)pSrc; // -> Step 5 puts 32 bits on the data line
*(uint64_t *)pDst = *(uint64_t *)pSrc; // -> converted to two 32-bit writes with chip select going inactive between them

memcpy() did not help.

After four Bytes step 5 is aborted and chip select returns inactive.
This results in very low performance, since before the QSPI flash device will accept another
write access I have to issue a WriteEnable command which is not possible in memory mapped mode.
So I even cannot use EDMA to write more than 32bits of data at once.

Any ideas?

regards,
Markus

  • The RTOS team have been notified. They will respond here.
  • Markus,

    Yes, there appears to be an issue with QSPI LLD mmaped access that we are discussing on the E2E here:
    e2e.ti.com/.../2456039

    At the moment the flash driver seems to be written such that it programs a 32 bit word at a time and this is causing the reason for the poor performance. 

    Regards,

    Rahul

  • Hi Rahul

    Thank you for the other link.
    I just had a look at the corrected S25FL.c file.
    I have not tested it on real hardware, but as far as I can see this only corrects the driver so that it is working at all.
    But the performance problems (only 32 bits written to qspi flash at a time) still remains as the underlaying qspi
    driver is not changed.

    My questions about transferring more than 32 bits in memory mapped mode go beyond driver implementation.
    The question is if *any* driver implementaion has a chance to overcome the 32 bit limit.
    When I address the qspi module bare metal I'm also not able to output more than 32 bits.
    The QSPI_SPI_SETUP<n>_REG registers, used to configure transfers in memory mapped mode have no
    field to set the word length. The only register where I can set a word length is QSPI_SPI_CMD_REG.
    Setting word length in that register prior to memory mapped transfer seems to have no effect.
    The final question is if I'm doing something wrong (and if yes, what) or if it is not possible by hardeware design
    to overcome the 32bit read/write limit in memory mapped mode?

    regards,
    Markus

  • Here is the response from the QSPI designer regarding this issue which may help other users running into this issue QSPI memory mapped mode.

    QSPI 32 bit write restriction is a known limitation of QSPI memory map transfers. In memory mapped write, WE (write enable) has to be sent every time after every 32 bites (4-byte). Reason to this was because the module was focused primarily on read operation and thus there exists this limitation for bare minimum write.

    To compensate for this limitation and achieve better throughput, it is recommended to enable the EDMA for maximum 128-bytes burst size transfer for communication between EDMA-QSPI. This will also alleviate the CPU for bandwidth to do additional processing. However, customer should note that the throughput will still be limited by 7 dead cycles after each 128 bytes transfer, and need to re-enable WE.
  • Hi Rahul

    Thank you for this answer.
    At the moment I unfortunately dont have time to check the EDMA read transfer via memory mapped port.
    Is there any QSPI example which uses EDMA?

    Regards,
    Markus
  • We currently have only MCSPI implementation of the SPI LLD with the EDMA.