Part Number: 66AK2H14
Hi,
66AK2H14 is interfaced to Altera MAX10 series CPLD through EMIF16 interface.
66AK2H14 runs at 800MHz. Hence EMIF16 @ 133.3MHz
EMIF16 is configured to Select Strobe Mode.
We have to perform CPLD read/write through EMIF16 at 200Mbps
There are 2 different Timing diagrams - in EMIF16 user guide spruza.pdf
Figure 2-4 Asynchronous Read Timing Diagram
Figure 2-5 Asynchronous Write Timing Diagram
Figure 2-6 Asynchronous Read Cycle (Select Strobe mode)
Figure 2-7 Write Cycle (Select Strobe Mode)
and there is another timing diagram in 66AK2H14 data sheet
Figure 11-53. EMIF16 Asynchronous Memory Read Timing Diagram
Figure 11-54. EMIF16 Asynchronous Memory Write Timing Diagram
Q1: Which one has to be refered for the present scenario.
Q2: What is the maximum throughput that was achieved using EMIF16 - FPGA/CPLD If you have any tested data.
Regards,
Mahima Shanbag
