• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 99 subscribers
  • Views 1310 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMDSICE3359: EtherCAT distributed clock latching

Ian Prochazka
Prodigy 30 points
Part Number: TMDSICE3359
Other Parts Discussed in Thread: AM3359, AM3357

Hello Ti Support and everybody. We need to create EtherCAT slave node that should be capable of latching EtherCAT distributed clock time stamps on digital input edges. We are looking for solution that would support timestamp latching on at least 16 digital inputs that may be changing virtually simultaneously. Latching delay has to be under 1us.  I wonder whether Sitara Processor AM3357 and/or AM3359 can do that ? Thank you, Ian

  • 0
    TI__Guru**** 393215 points
    The RTOS team has been notified. Please expect them to reply here next week, as the person involved is currently travelling.
  • 0 in reply to Biser Gatchev-XID
    TI__Mastermind 43296 points
    Hi Ian,

    Can you take a look if the thread helps: e2e.ti.com/.../2013866 ?
    Let me check if we have latching delay measurement internally. With 1us delay requirement and 5ns instruction cycle in PRU, AM335x should have no problem to support it.

    Regards,
    Garrett
  • 0 in reply to Garrett Ding
    TI__Mastermind 43296 points
    Hi Ian,

    We don't have the specific measurement here. In terms of the latching delay, is this time stamping jitter or latency from IO toggle to timestamp capture?

    Also, you may have noticed we have 2 latch input pins per ICSS, will it be from 2 of the '16 digital inputs'?

    Regards,
    Garrett
  • 0 in reply to Garrett Ding
    Prodigy 30 points

    Thank you Garrett for your both responses.

    With respect to the 1us "latching delay", I have meant the latency from IO toggle to timestamp capture. However the same can probably apply to the jitter as well. 1us was only to have some number to start with, lower values of both would of course be better.  

    I am not sure that I understood properly the second question " will it be from 2 of the '16 digital inputs'? " If the ICSS has only two latching inputs, the implementation would have to route various inputs into those two ones and read quickly latched data so that the ICSS could be re-arm to capture the next one. How quickly that could be done?
    The other option that came to my mind would be to get 'somehow' the distributed clock out of the ICSS and implement latching outside the ICSS.
    That was the point of the question. To see whether a knowledgeable expert would consider the requirements of  latching DC timestamps of at least 16 digital inputs with less then 1us latency doable with Sitara or not. And if so, what approach he/she would recommend. Then we, as outsiders, will step in and will try to do it. We may not see the dead end, that is why I seek an input from experts first.

    Thank you,
    Ian

  • 0 in reply to Ian Prochazka
    TI__Mastermind 40580 points

    Hi Ian,

    If I am understanding correctly, you need accurate timestamp for your 16 digital inputs. An idea could be to use IEP counter for this instead of Latch0/1.

    From Beckhoff  DC information I see:

    Reaction to an external signal: Capture - Latch 0/1

    If an ESC is configured accordingly it can store the current local time if an external event occurs, i.e. it can place it into a buffer without delay using a capture unit. Examples for such external events are: arrival of the EtherCAT frame, end of the EtherCAT frame, edge on a dedicated pin of the ESC, communication with a connected microcontroller, and a wide range of other options.

    From there, I think latch 0/1 is used to add timestamps (or action) after an external EtherCAT event (ex EtherCAT frame). For other events, such ar DIs, you could use SoC timers

    On the other hand, about your “latch delay” there are some registers that you can check. More information here: Beckhoff Syncronization modes EtherCAT slave

    thank you,

    Paula

  • 0 in reply to Paula Carrillo
    Prodigy 30 points

    Hello Paula,

    thank you for response.

    I am not sure though, whether I understood your idea correctly. Did you mean to configure IEP counter to run synchronously with EthetCAT DC and then implement capturing IEP counter time? Because we need timestamps of the digital input edges in DC time that then need to be communicated to EtherCAT master (Sitara would implement EtherCAT slave)

    Best regards,
    Ian

  • 0 in reply to Ian Prochazka
    TI__Mastermind 40580 points

    Hi Ian, I was checking with some colleagues, and there are 3 eCAPs in the SoC that you can use for time stamps + 2 latch from PRU-ICSS. So, that would be 5. I am afraid it is not possible to have 16 timestamps of the digital input.
     
    Thank you,
    Paula