Please Clarify How Multiple HWIs Behave

MattB

Expert 2025 points

Hi,

I'm just reading and thinking about HWIs.

I'm thinking of using three HWIs to handle asynchronous events.

As I understand it the DSP/BIOS dispatcher enables interrupts which means HWI functions can themselves be interrupted.

The nesting of interrupt functions can be controlled using the interrupt mask.

If I specify an interrupt mask other than "all" then do lower priority interrupts interrupt higher priority ones? In other words, if I have an INT4 handler that is perhaps a bit long will it get interrupted if an INT5 occurs before it has finished?

Thanks,

Matt

over 15 years ago

0 David Friedland over 15 years ago

TI__Mastermind 18320 points

Matt,

The interrupt priority that is implemented on the chip is relevant only to pending interrupts. Once you are servicing an interrupt, you will need to use the mask as a mechanism to control which interrupts will preempt a currently running ISR (and therefore have a higher "priority" than the one running).

Dave

0 MattB over 15 years ago in reply to David Friedland

Expert 2025 points

Hi Dave,

David Friedland said:
Once you are servicing an interrupt, you will need to use the mask as a mechanism to control which interrupts will preempt a currently running ISR (and therefore have a higher "priority" than the one running).

And therefore by default (interruptMask = "self") any new interrupt will preempt a running ISR.(??)

Thanks,

Matt

0 David Friedland over 15 years ago in reply to David Friedland

TI__Mastermind 18320 points

BTW, I found a relevant documentation:

TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide

5.7.2 Nested Interrupts
Generally, when the CPU enters an interrupt service routine, interrupts are disabled. However, when the
interrupt service routine is for one of the maskable interrupts (INT4-INT15), an NMI can interrupt
processing of the maskable interrupt. In other words, an NMI can interrupt a maskable interrupt, but
neither an NMI nor a maskable interrupt can interrupt an NMI.
Also, there may be times when you want to allow an interrupt service routine to be interrupted by another
(particularly higher priority) interrupt. Even though the processor by default does not allow interrupt service
routines to be interrupted unless the source is an NMI, it is possible to nest interrupts under software
control.

0 David Friedland over 15 years ago in reply to MattB

TI__Mastermind 18320 points

And therefore by default (interruptMask = "self") any new interrupt will preempt a running ISR.(??)

Correct, Hwi.MaskingOption_SELF means that only this interrupt is disabled.

0 MattB over 15 years ago in reply to David Friedland

Expert 2025 points

Thanks!

As an aside where does the terminology and/or code "Hwi.MaskingOption_SELF" come from?

0 David Friedland over 15 years ago in reply to MattB

TI__Mastermind 18320 points

Depends. What version of BIOS are you using?

0 MattB over 15 years ago in reply to David Friedland

Expert 2025 points

David Friedland said:
What version of BIOS are you using?

Oh, V5.41.06.21...

but I think I see where this is going!

Thanks,

Matt

0 David Friedland over 15 years ago in reply to MattB

TI__Mastermind 18320 points

My reference to Hwi.MaskingOption_SELF was for BIOS 6. BIOS 5 uses the IERMASK and I believe that "self" is simply the default.

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Please Clarify How Multiple HWIs Behave