TMS320C6747: GPIO interrupt

The team is notified. They will post their feedback directly here.

BR
Tsvetolin Shulev

Hi Tsvetolin,

Thank you for your support.
I am waiting for their feedback.

Best Regards,
Kanae

Hi Kanae,

Please confirm the DVDD IO voltage is 3.3V

Kanae said:

recommended value for the most low level

According to Table 5.3 Recommended Operating Conditions in the datasheet (SPRS377F), VIL <= 0.8 when DVDD = 3.3V. DVDD IO voltage appears to be limited to 3.3V in the datasheet.

It would be best if Vil < = 0.2V and transition time is as fast as possible.

Kanae said:

and the rising time

The datasheet does not specify a rise time for the GPIO edge dectection. Instead it specifies a low pulse duration and a high pulse duration. Each must be at least two cycles of the SYSCLK4 clock (SYSCLK / 4). The low pulse duration begins after the signal crosses the VIL threshold and the high pulse duration begins after the signal crosses the VIH threshold. This makes me believe that the edge detection logic is based on the changing level of the GPIO input. I will confirm internally.

Kanae said:

It sets the rising edge interrupt, however the interrupt doesn't occur on the DSP side occasionally
even if it generates the interrupt signal.

Q: Can you please confirm?

1) You mean that the signal going into the GPIO transitions from low to high, but sometimes there is no interrupt, or...

2) Is the interrupt bit always getting set after a low to high transition, but the CPU sometimes does not execute the interrupt service routine?

Q: What silicon revision is this issue occuring on?

Refer to TMS320C6747 Errata (SPRZ284G) Advisory 1.1.16 Vil on 3.3V LVCMOS Input Buffers

- It would be best if Vil < = 0.2V and transition time is as fast as possible.

Interrupt requests within each bank are combined.

Q: Are there any other pins within the same bank configured to trigger interrupts?

Q: Is there any change in the INTSTATx register for its bank after the rising edge?

The ISR should not require critical section protection in the ISR...

Q: Could the ISR have gotten interrupted by another interrupt?

Q: Does software keeps interrupts globally enabled?

"Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to anther process during GPIO programming)."

GPIO Banks 0, 1, 2, 3, 4, 5, 6, and 7 Interrupts assigned to DSP Events 65, 41, 49, 52, 54, 59, 62 and 72 respectively

Q: Can they sanity check that there is no issue with the pinmux selecting something other than GPIO?

Q: Finally, as a debugging step, can they configure the GPIO as an output to test interrupt generation on the rising edge transition of the GPIO output?

Hope this helps,
Mark

[EDIT - DVDD IO voltage is limited to 3.3V on this device, removed 1.8V]

Hi Mark,
Thank you for your reply.

I will ask your check items to my customer except for their silicon revision.

Q: What silicon revision is this issue occurring on?
A: TMS320C6747DZKB3(Rev.3.0)


Regarding some your comments, I would like to make sure the following items.

- "Vil < = 0.2V" in your post, is this meant "Vol < = 0.2V"? Typo?


Best regards,
Kanae