TDA2EG-17: Dose QSPI clock mode 3 TDA2EG-17 data input QSPI memory at clock rising edge or falling edge?

Tao Han

Part Number: TDA2EG-17
Other Parts Discussed in Thread: TDA2E

Hi Expert:

At TDA2E-17 TRM, 32.3.7.5 ROM boot introduce said that QSPI 4-bits mode, TDA2E-17 use clock mode 3 read/write data.

It means TDA2E capture data input at rising edge of QSPI_CLK and send out data to memory at falling edge of QSPI_CLK.

But at 24.5.4.1.6 QSPI table 24-359 it said mode 3, TDA2E capture data at falling edge of QSPI_CLK.

We have checked EVM board used spansion QSPI memory, TDA2E need capture data at rising edge of QSPI_CLK, then it can work.

Please help us check TDA2E work at 4-bits QSPI mode 3, capture data at rising edge of QSPI_CLK or falling edge?

Best Regards!

han tao

0 Stanislav Stilyanov over 7 years ago

Hi Tao,

Looks like this is explained in a small footnote in the Data Manual doc:

3) The Device captures data on the falling clock edge in Clock Mode 0 and 3, as opposed to the traditional rising clock edge. Although

nonstandard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that

launch data on the falling edge in Clock Modes 0 and 3.

Regards,

Stan

0 Tao Han over 7 years ago in reply to Stanislav Stilyanov

Hi Stan:

Thanks for clarify it.
I will check whether customer has configure QSPI IO delay follow our DM 5.9.6.13 part.
Best Regards!
han tao

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