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Using AEMIF OneNAND bust mode to improve throughput.

Brian Lust
Prodigy 40 points

Exploring setting the AEMIF in OneNAND synchronous mode (continuous linear burst) to increase read throughput, but use an fpga at the other end of the bus instead of a OneNAND device.

If using the EDMA controller to set up the read, what is the maximum number of bytes that could be transferred in the burst?  Which device will be the limiting factor? 

There is not much information on the OneNAND mode other than it doesn't support wrap burst modes.  What terminates the continuous burst read?

 

 

  • 0
    TI__Expert 5955 points

    The EDMA controller can handle a very large number of bytes that could be transfered in a single burst (ACOUNT, BCOUNT and CCOUNT). The FPGA will be the limiting factor since it is the one to allow how many data can be burst at a time. I am not sure if the AEMIF has the maximum burst in synchronous mode. It might breaks up into 32 byte transfers. Let me get back to you on this. The CE should go back up high to terminate the burst read.

    Thanks,

    -Tai Nguyen   

  • 0 in reply to Tai Nguyen
    Prodigy 40 points

    Thanks for the reply.  I intend to construct the FPGA logic to handle the maximum burst length supported by the AEMIF.  Though I have never worked with OneNAND, it appears that those devices support up to 512 byte transfers in addition to 4, 8, 16, and 32 byte bursts. 

    I very much hope the AEMIF in OneNAND mode supports the 512 byte burst length as well, and look forward to your further reply on this subject.

     

    Regards,

    Brian Lust

  • 0 in reply to Brian Lust
    TI__Expert 5955 points

    Hi Brian,

    Just want to let you know that I am working on this post. I got a partial answer. The AEMIF can handle up to a max of 1024-byte burst. I am still checking to see if the max burst is broken down to smaller burst chunks or not. I will let you know if it is not.

    Thanks and regards,

    Tai Nguyen

  • 0 in reply to Tai Nguyen
    TI__Expert 5955 points

    Hi Brian,

    Further checking I found that depend on the master the max burst will be broken down to smaller burst chunk due to the limit bus size of the master. If the EDMA is being used, it is basically continuous burst.  If the CPU is doing the transfer, it will be 32bit word transfer at a time with gaps between each word transfer.  The CPU just does 32bit word transfer. 

    The bridges will break the transfer up if it has to, but that’s dependent on source and destination of the data path.  For example, the bridges breaks up the EDMA transfer, but the EDMA is faster with a bigger data width (64bits) that it can continuously read or write from the AEMIF.

    Hope this helps.

    -Tai nguyen