This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

66AK2H14: Performing On-Chip Byte-Error Rate (BER) Testing

Part Number: 66AK2H14


We are using the PRBS Generator and Checker referring to the following but do not understand why the BER can be tested.

Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A)
http://www.ti.com/lit/ug/spruho3a/spruho3a.pdf
19.1.5 Performing On-Chip Byte-Error Rate (BER) Testing (Page 151)

C:\ti\pdk_k2hk_4_0_7\packages\ti\diag\serdes_diag\test\k2h\c66\serdes_diag_test.c

In step 10, BIST_CHK_SYNCH is used to check successfully detected the PRBS data. I want to know more about the conditions when BIST_CHK_SYNCH is asserted.

Does BIST_CHK_SYNCH continue to be asserted while the PRBS pattern transmitted from the PRBS generator matches the correct polynomial?
Does BIST_CHK_SYNCH continue to be de-asserted while the pattern does not match?

In step 15, verifying that BIST_CHK_ERRORS is 0 verifies that no bit errors were measured during the testing sequence.

If BIST_CHK_ERRORS is nonzero, how can the BER be calculated?

Best regards,

Daisuke