• State Answer Suggested
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 342 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Timing of the 5509A interrupt

Tony Ranson
Prodigy 190 points

I have a couple of questions:

Does anyone know how many CPU clock cycles pass from when the interrupt is enable or disabled through status register (INTM) until the actual interrupt enable or disable takes effect?

What is the interrupt latency for internally generated interrupts (e.g. from the DMA controller)?

Thank you in advance.

Tony

 

  • 0
    Intellectual 390 points

    The DSP needs to see the INT pin low on three successive clock cycles to register an interrupt, so that's the lower bound. On my 5509A system, I'm seeing 11-12 clock cycles between the falling edge of INT and the external DMA fetch it triggers. Some of that time is certainly taken up in the DMA subsystem.

    David L. Rick

    Hach Company