Part Number: AM3358
Tool/software: TI-RTOS
I am attempting to configure PWMSS0, PWMSS1, and PWMSS2. I'm currently using a Beaglebone Black board as a platform, but will be migrating to a custom board based on the Sitara A8 in future. I'm using CCS 7.4.0.00015 as my IDE. I have setup the pwmss_ctrl regsister to enable clock to each of the PWMSSx modules by writing a 1 to pwmss0_tbclken, pwmss1_tbclken, and pwmss2_tbclken and have confirmed this by viewing the memory in CCS. I am able to setup and use PWMSS0 without issue. I can view all of the memory related to PWMSS0 without issue. I am also able to view all of the memory related to PWMSS2 (0x48304000) without problem.
When I attempt to configure PWMSS1 using the system function CSL_epwmTbTimebaseClkCfg(SOC_PWMSS1_REGS, TBCLK_FREQ, MODULE_CLK); my project immediately crashes. When I attempt to view the memory at 0x48302000 prior to this call, all locations come back as "????????". When I attempt to view the ePWMSS1 registers in CCS using the Registers window, CCS reports "ERROR: Unable to read". The MMU has been mapped to handle the memory locations.
Can you provide assistance with this? Per the sample code from TI and the Sitara Technical Reference (spruh73p.pdf) it appears PWMSS1 should be functioning correctly, as PWMSS0 did. However, any attempt to access the configuration register at 0x48302000 results in an immediate fault and exit.
Thanks.
Tim Cleveland