This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RTOS/AM3358: Cannot enable PWMSS1

Part Number: AM3358

Tool/software: TI-RTOS

I am attempting to configure PWMSS0, PWMSS1, and PWMSS2. I'm currently using a Beaglebone Black board as a platform, but will be migrating to a custom board based on the Sitara A8 in future. I'm using CCS 7.4.0.00015 as my IDE. I have setup the pwmss_ctrl regsister to enable clock to each of the PWMSSx modules by writing a 1 to pwmss0_tbclken, pwmss1_tbclken, and pwmss2_tbclken and have confirmed this by viewing the memory in CCS. I am able to setup and use PWMSS0 without issue. I can view all of the memory related to PWMSS0 without issue. I am also able to view all of the memory related to PWMSS2 (0x48304000) without problem. 

When I attempt to configure PWMSS1 using the system function  CSL_epwmTbTimebaseClkCfg(SOC_PWMSS1_REGS, TBCLK_FREQ, MODULE_CLK); my project immediately crashes. When I attempt to view the memory at 0x48302000 prior to this call, all locations come back as "????????". When I attempt to view the ePWMSS1 registers in CCS using the Registers window, CCS reports "ERROR: Unable to read". The MMU has been mapped to handle the memory locations.

Can you provide assistance with this? Per the sample code from TI and the Sitara Technical Reference (spruh73p.pdf) it appears PWMSS1 should be functioning correctly, as PWMSS0 did. However, any attempt to access the configuration register at 0x48302000 results in an immediate fault and exit.

Thanks.

Tim Cleveland

  • The RTOS team have been notified. They will respond here.
  • A search of E2E turned up the following thread of the same problem, dated March 2017:
    e2e.ti.com/.../573789

    I took the information that poster provided and went digging. I found the same issue in pdk_am335x_1_0_9: PWMSS1 is not enabled by
    the SOC starterware/driver code provided by TI. Within the file am335x_prcm.c, I found the following:

    am335x_prcm.c is located in: pdk_am335x_1_0_9\packages\ti\starterware\soc\am335x

    #if defined(BUILDCFG_MOD_PWMSS)
    case CHIPDB_MOD_ID_PWMSS:
    {
    switch(instNum)
    {
    case 0:
    enableModule(SOC_CM_PER_REGS, CM_PER_EPWMSS0_CLKCTRL,
    CM_PER_L4LS_CLKSTCTRL,
    CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK);
    break;
    case 2:
    enableModule(SOC_CM_PER_REGS, CM_PER_EPWMSS2_CLKCTRL,
    CM_PER_L4LS_CLKSTCTRL,
    CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK);
    break;
    }
    }
    break;
    #endif /* #if defined(BUILDCFG_MOD_PWMSS) */


    I modified am335x_prcm.c as follows:

    #if defined(BUILDCFG_MOD_PWMSS)
    case CHIPDB_MOD_ID_PWMSS:
    {
    switch(instNum)
    {
    case 0:
    enableModule(SOC_CM_PER_REGS, CM_PER_EPWMSS0_CLKCTRL,
    CM_PER_L4LS_CLKSTCTRL,
    CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK);
    break;

    case 1:
    enableModule(SOC_CM_PER_REGS, CM_PER_EPWMSS1_CLKCTRL,
    CM_PER_L4LS_CLKSTCTRL,
    CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK);
    break;

    case 2:
    enableModule(SOC_CM_PER_REGS, CM_PER_EPWMSS2_CLKCTRL,
    CM_PER_L4LS_CLKSTCTRL,
    CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK);
    break;
    }
    }
    break;
    #endif /* #if defined(BUILDCFG_MOD_PWMSS) */


    After updating am335x_prcm.c, I then had to bring the change into my project. To do this I had:
    1. Rebuild the SOC from the command line:
    c:\ti\xdctools_3_50_03_33_core> xdc.exe -P c:/ti/pdk_am335x_1_0_9/packages/ti/starterware/soc

    2. I then had to rebuild the board files. Remember to setup the environment variables before attempting this:
    c:\ti\pdk_am335x_1_0_9\packages> gmake board_lib LIMIT_BOARDS=bbbAM335x BUILD_PROFILE=debug

    These two steps thus brought in the update to am335x_prcm.c and updated my board files. I was then (finally) able to rebuild my project via CCS and low and behold, it works. I am now able to use PWMSS1.

    Questions:

    1. I based my fix off your existing code. Do you have any issues with what I have implemented?

    2. Why hasn't this bug/omission in the SOC files been corrected since the original post from March 2017?
    If you're not going to fix it, then why hasn't a document been provided by TI listing what is and is not enabled within your starterware/driver code provided for Sitara in non-Linux environments?

    - Tim Cleveland
  • Tim,

    Thanks for your patience in digging into the issue.

    1) No issues, it looks correct.
    2) I should have done a better job following up on the previous post you pointed to, to ensure we had it documented.
    Having said that, there is an entry now in the Processor SDK FAQ under board support section processors.wiki.ti.com/.../Processor_SDK_RTOS_FAQ

    Thank you for taking the time to post your solution in detail.

    Lali