Hi,
I am trying to evaluate Latency of access remote DSP through Hyperlink .
In a TI evaluation document,/cfs-file/__key/communityserver-discussions-components-files/791/3527.HyperLink_5F00_Programming_5F00_and_5F00_Performance_5F00_consideration.pdf
It's found in Figure 4, Figure 5, Figure 6 DSP core load/store on remote DSP DDR, SL2, LL2 respectively, the LLDW Without Cache latency will be upto 250 or more cycles/access when memory stride is 1 or 8 Byte.
May I know why? Without Cache, should it be the same for any stride? Any reason for the smaller the stride is, the longer the Latency is?
Thanks a lot.
